linux/Documentation/admin-guide/perf, branch v6.8

docs: perf: Add description for Synopsys DesignWare PCIe PMU driver

2023-12-13T13:35:41Z

Alibaba's T-Head Yitan 710 SoC includes Synopsys' DesignWare Core PCIe controller which implements PMU for performance and functional debugging to facilitate system maintenance. Document it to provide guidance on how to use it. Signed-off-by: Shuai Xue Reviewed-by: Baolin Wang Reviewed-by: Jonathan Cameron Reviewed-by: Yicong Yang Tested-by: Ilkka Koskinen Link: https://lore.kernel.org/r/20231208025652.87192-2-xueshuai@linux.alibaba.com Signed-off-by: Will Deacon

docs/perf: Add explanation for DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER quirk

2023-12-05T14:12:07Z

Add explanation for DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER quirk. Signed-off-by: Xu Yang Link: https://lore.kernel.org/r/20231120093317.2652866-2-xu.yang_2@nxp.com Signed-off-by: Will Deacon

docs/perf: Add ampere_cspmu to toctree to fix a build warning

2023-10-12T11:32:36Z

Add ampere_cspmu to toctree in order to address the following warning produced when building documents: Documentation/admin-guide/perf/ampere_cspmu.rst: WARNING: document isn't included in any toctree Reported-by: Stephen Rothwell Closes: https://lore.kernel.org/all/20231011172250.5a6498e5@canb.auug.org.au/ Fixes: 53a810ad3c5c ("perf: arm_cspmu: ampere_cspmu: Add support for Ampere SoC PMU") Signed-off-by: Ilkka Koskinen Link: https://lore.kernel.org/r/20231012074103.3772114-1-ilkka@os.amperecomputing.com Signed-off-by: Will Deacon

perf: arm_cspmu: ampere_cspmu: Add support for Ampere SoC PMU

2023-10-10T18:10:54Z

Ampere SoC PMU follows CoreSight PMU architecture. It uses implementation specific registers to filter events rather than PMEVFILTnR registers. Signed-off-by: Ilkka Koskinen Link: https://lore.kernel.org/r/20230913233941.9814-5-ilkka@os.amperecomputing.com [will: Include linux/io.h in ampere_cspmu.c for writel()] Signed-off-by: Will Deacon

perf docs: Update metric usage for Alibaba's T-Head PMU driver (arm64)

2023-07-28T22:01:17Z

Alibaba's T-Head ali_drw PMU supports DDR bandwidth metrics. Update its usage in the documentation. Reviewed-by: John Garry Signed-off-by: Jing Zhang Acked-by: Ian Rogers Cc: Namhyung Kim Cc: Shuai Xue Cc: Will Deacon Cc: Zhuo Song Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Link: https://lore.kernel.org/r/1690528175-2499-4-git-send-email-renyu.zj@linux.alibaba.com Signed-off-by: Arnaldo Carvalho de Melo

Merge tag 'cxl-for-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl

2023-07-01T15:58:41Z

Pull CXL updates from Dan Williams: "The highlights in terms of new functionality are support for the standard CXL Performance Monitor definition that appeared in CXL 3.0, support for device sanitization (wiping all data from a device), secure-erase (re-keying encryption of user data), and support for firmware update. The firmware update support is notable as it reuses the simple sysfs_upload interface to just cat(1) a blob to a sysfs file and pipe that to the device. Additionally there are a substantial number of cleanups and reorganizations to get ready for RCH error handling (RCH == Restricted CXL Host == current shipping hardware generation / pre CXL-2.0 topologies) and type-2 (accelerator / vendor specific) devices. For vendor specific devices they implement a subset of what the generic type-3 (generic memory expander) driver expects. As a result the rework decouples optional infrastructure from the core driver context. For RCH topologies, where the specification working group did not want to confuse pre-CXL-aware operating systems, many of the standard registers are hidden which makes support standard bus features like AER (PCIe Advanced Error Reporting) difficult. The rework arranges for the driver to help the PCI-AER core. Bjorn is on board with this direction but a late regression disocvery means the completion of this functionality needs to cook a bit longer, so it is code reorganizations only for now. Summary: - Add infrastructure for supporting background commands along with support for device sanitization and firmware update - Introduce a CXL performance monitoring unit driver based on the common definition in the specification. - Land some preparatory cleanup and refactoring for the anticipated arrival of CXL type-2 (accelerator devices) and CXL RCH (CXL-v1.1 topology) error handling. - Rework CPU cache management with respect to region configuration (device hotplug or other dynamic changes to memory interleaving) - Fix region reconfiguration vs CXL decoder ordering rules" * tag 'cxl-for-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (51 commits) cxl: Fix one kernel-doc comment cxl/pci: Use correct flag for sanitize polling docs: perf: Minimal introduction the the CXL PMU device and driver perf: CXL Performance Monitoring Unit driver tools/testing/cxl: add firmware update emulation to CXL memdevs tools/testing/cxl: Use named effects for the Command Effect Log tools/testing/cxl: Fix command effects for inject/clear poison cxl: add a firmware update mechanism using the sysfs firmware loader cxl/test: Add Secure Erase opcode support cxl/mem: Support Secure Erase cxl/test: Add Sanitize opcode support cxl/mem: Wire up Sanitization support cxl/mbox: Add sanitization handling machinery cxl/mem: Introduce security state sysfs file cxl/mbox: Allow for IRQ_NONE case in the isr Revert "cxl/port: Enable the HDM decoder capability for switch ports" cxl/memdev: Formalize endpoint port linkage cxl/pci: Unconditionally unmask 256B Flit errors cxl/region: Manage decoder target_type at decoder-attach time cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM ...

docs: perf: Minimal introduction the the CXL PMU device and driver

2023-06-26T00:47:09Z

Very basic introduction to the device and the current driver support provided. I expect to expand on this in future versions of this patch set. Reviewed-by: Dave Jiang Reviewed-by: Kan Liang Signed-off-by: Jonathan Cameron Link: https://lore.kernel.org/r/20230526095824.16336-6-Jonathan.Cameron@huawei.com Signed-off-by: Dan Williams

docs: perf: Fix warning from 'make htmldocs' in hisi-pmu.rst

2023-06-19T10:02:18Z

Building the 'htmldocs' target results in the following warning when processing 'hisi-pmu.rst': | Documentation/admin-guide/perf/hisi-pmu.rst:107: ERROR: Unexpected indentation. Fix the warning by converting all of the register bitfield lists into proper bulleted lists and adjusting the indentation of the wrapping line accordingly. At the same time, use an enumerated list to describe the new PMUv2 functions. Fixes: ea8d1c062a0e ("docs: perf: Add new description for HiSilicon UC PMU") Reported-by: Stephen Rothwell Signed-off-by: Will Deacon

docs: perf: Add new description for HiSilicon UC PMU

2023-06-16T11:27:38Z

A new function is added on HiSilicon uncore UC PMU. The UC PMU support to filter statistical information based on the specified tx request uring channel. Make user configuration through "uring_channel" parameter. Document them to provide guidance on how to use them. Signed-off-by: Junhao He Reviewed-by: Jonathan Cameron Reviewed-by: Yicong Yang Acked-by: Mark Rutland Link: https://lore.kernel.org/r/20230615125926.29832-4-hejunhao3@huawei.com Signed-off-by: Will Deacon

Documentation: admin-guide: correct spelling

2023-02-02T18:04:42Z

Correct spelling problems for Documentation/admin-guide/ as reported by codespell. Signed-off-by: Randy Dunlap Reviewed-by: Mukesh Ojha Cc: Tejun Heo Cc: Zefan Li Cc: Johannes Weiner Cc: cgroups@vger.kernel.org Cc: Alasdair Kergon Cc: Mike Snitzer Cc: dm-devel@redhat.com Cc: Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org Cc: linux-mm@kvack.org Link: https://lore.kernel.org/r/20230129231053.20863-2-rdunlap@infradead.org Signed-off-by: Jonathan Corbet