<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/Documentation/devicetree/bindings/crypto, branch master</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=master</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2026-03-15T04:23:12Z</updated>
<entry>
<title>dt-bindings: crypto: inside-secure,safexcel: add compatible for MT7981</title>
<updated>2026-03-15T04:23:12Z</updated>
<author>
<name>Aleksander Jan Bajkowski</name>
<email>olek2@wp.pl</email>
</author>
<published>2026-03-03T18:53:49Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1e84df6ccfcb342262b02dfdb723eaad50a0b6c9'/>
<id>urn:sha1:1e84df6ccfcb342262b02dfdb723eaad50a0b6c9</id>
<content type='text'>
The MT7981 as well as the MT7986 have a built-in EIP-97 crypto accelerator.
This commit adds a compatible string for MT7981.

Signed-off-by: Aleksander Jan Bajkowski &lt;olek2@wp.pl&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@oss.qualcomm.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>dt-bindings: crypto: qcom,inline-crypto-engine: Document the Eliza ICE</title>
<updated>2026-03-07T05:12:20Z</updated>
<author>
<name>Abel Vesa</name>
<email>abel.vesa@oss.qualcomm.com</email>
</author>
<published>2026-02-23T08:44:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=618195a7ac3dfb88ef7ff701439cabcba2096f31'/>
<id>urn:sha1:618195a7ac3dfb88ef7ff701439cabcba2096f31</id>
<content type='text'>
Document the Inline Crypto Engine (ICE) on the Eliza platform.

Signed-off-by: Abel Vesa &lt;abel.vesa@oss.qualcomm.com&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@oss.qualcomm.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>dt-bindings: crypto: ice: add operating-points-v2 property for QCOM ICE</title>
<updated>2026-02-28T03:54:14Z</updated>
<author>
<name>Abhinaba Rakshit</name>
<email>abhinaba.rakshit@oss.qualcomm.com</email>
</author>
<published>2026-02-19T09:39:13Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1eb6c478f1edc4384d8fea765cd13ac01199e8b5'/>
<id>urn:sha1:1eb6c478f1edc4384d8fea765cd13ac01199e8b5</id>
<content type='text'>
Add support for specifying OPPs for the Qualcomm Inline Crypto Engine
by allowing the use of the standard "operating-points-v2" property in
the ICE device node.

ICE clock management was handled by the storage drivers in legacy
bindings, so the ICE driver itself had no mechanism for clock scaling.
With the introduction of the new standalone ICE device node, clock
control must now be performed directly by the ICE driver. Enabling
operating-points-v2 allows the driver to describe and manage the
frequency and voltage requirements for proper DVFS operation.

Acked-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Signed-off-by: Abhinaba Rakshit &lt;abhinaba.rakshit@oss.qualcomm.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>Merge tag 'devicetree-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux</title>
<updated>2026-02-12T02:27:08Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-02-12T02:27:08Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=098b6e44cbaa2d526d06af90c862d13fb414a0ec'/>
<id>urn:sha1:098b6e44cbaa2d526d06af90c862d13fb414a0ec</id>
<content type='text'>
Pull devicetree updates from Rob Herring:
 "DT core:

   - Sync dtc/libfdt with upstream v1.7.2-62-ga26ef6400bd8

   - Add a for_each_compatible_node_scoped() loop and convert users in
     cpufreq, dmaengine, clk, cdx, powerpc and Arm

   - Simplify of/platform.c with scoped loop helpers

   - Add fw_devlink tracking for "mmc-pwrseq"

   - Optimize fw_devlink callback code size for pinctrl-N properties

   - Replace strcmp_suffix() with strends()

  DT bindings:

   - Support building single binding targets

   - Convert google,goldfish-fb, cznic,turris-mox-rwtm, ti,prm-inst

   - Add bindings for Freescale AVIC, Realtek RTD1xxx system
     controllers, Microchip 25AA010A EEPROM, OnSemi FIN3385, IEI
     WT61P803 PUZZLE, Delta Electronics DPS-800-AB power supply,
     Infineon IR35221 Digital Multi-phase Controller, Infineon PXE1610
     Digital Dual Output 6+1 VR12.5 &amp; VR13 CPU Controller,
     socionext,uniphier-smpctrl, and xlnx,zynqmp-firmware

   - Lots of trivial binding fixes to address warnings in DTS files.
     These are mostly for arm64 platforms which is getting closer to be
     warning free. Some public shaming has helped.

   - Fix I2C bus node names in examples

   - Drop obsolete brcm,vulcan-soc binding

   - Drop unreferenced binding headers"

* tag 'devicetree-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (60 commits)
  dt-bindings: interrupt-controller: Add compatiblie string fsl,imx(1|25|27|31|35)-avic
  dt-bindings: soc: imx: add fsl,aips and fsl,emi compatible strings
  dt-bindings: display: bridge: lt8912b: Drop reset gpio requirement
  dt-bindings: firmware: fsl,scu: Mark multi-channel MU layouts as deprecated
  cpufreq: s5pv210: Simplify with scoped for each OF child loop
  dmaengine: fsl_raid: Simplify with scoped for each OF child loop
  clk: imx: imx31: Simplify with scoped for each OF child loop
  clk: imx: imx27: Simplify with scoped for each OF child loop
  cdx: Use mutex guard to simplify error handling
  cdx: Simplify with scoped for each OF child loop
  powerpc/wii: Simplify with scoped for each OF child loop
  powerpc/fsp2: Simplify with scoped for each OF child loop
  ARM: exynos: Simplify with scoped for each OF child loop
  ARM: at91: Simplify with scoped for each OF child loop
  of: Add for_each_compatible_node_scoped() helper
  dt-bindings: Fix emails with spaces or missing brackets
  scripts/dtc: Update to upstream version v1.7.2-62-ga26ef6400bd8
  dt-bindings: crypto: inside-secure,safexcel: Mandate only ring IRQs
  dt-bindings: crypto: inside-secure,safexcel: Add SoC compatibles
  of: reserved_mem: Fix placement of __free() annotation
  ...
</content>
</entry>
<entry>
<title>Merge tag 'soc-drivers-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc</title>
<updated>2026-02-11T04:45:30Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-02-11T04:45:30Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=bdbddf72a2ab1cfea699959795d70df3931eefe7'/>
<id>urn:sha1:bdbddf72a2ab1cfea699959795d70df3931eefe7</id>
<content type='text'>
Pull SoC driver updates from Arnd Bergmann:
 "There are are a number of to firmware drivers, in particular the TEE
  subsystem:

   - a bus callback for TEE firmware that device drivers can register to

   - sysfs support for tee firmware information

   - minor updates to platform specific TEE drivers for AMD, NXP,
     Qualcomm and the generic optee driver

   - ARM SCMI firmware refactoring to improve the protocol discover
     among other fixes and cleanups

   - ARM FF-A firmware interoperability improvements

  The reset controller and memory controller subsystems gain support for
  additional hardware platforms from Mediatek, Renesas, NXP, Canaan and
  SpacemiT.

  Most of the other changes are for random drivers/soc code. Among a
  number of cleanups and newly added hardware support, including:

   - Mediatek MT8196 DVFS power management and mailbox support

   - Qualcomm SCM firmware and MDT loader refactoring, as part of the
     new Glymur platform support.

   - NXP i.MX9 System Manager firmware support for accessing the syslog

   - Minor updates for TI, Renesas, Samsung, Apple, Marvell and AMD
     SoCs"

* tag 'soc-drivers-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (171 commits)
  bus: fsl-mc: fix an error handling in fsl_mc_device_add()
  reset: spacemit: Add SpacemiT K3 reset driver
  reset: spacemit: Extract common K1 reset code
  reset: Create subdirectory for SpacemiT drivers
  dt-bindings: soc: spacemit: Add K3 reset support and IDs
  reset: canaan: k230: drop OF dependency and enable by default
  reset: rzg2l-usbphy-ctrl: Add suspend/resume support
  reset: rzg2l-usbphy-ctrl: Propagate the return value of regmap_field_update_bits()
  reset: gpio: check the return value of gpiod_set_value_cansleep()
  reset: imx8mp-audiomix: Support i.MX8ULP SIM LPAV
  reset: imx8mp-audiomix: Extend the driver usage
  reset: imx8mp-audiomix: Switch to using regmap API
  reset: imx8mp-audiomix: Drop unneeded macros
  soc: fsl: qe: qe_ports_ic: Consolidate chained IRQ handler install/remove
  soc: mediatek: mtk-cmdq: Add mminfra_offset adjustment for DRAM addresses
  soc: mediatek: mtk-cmdq: Extend cmdq_pkt_write API for SoCs without subsys ID
  soc: mediatek: mtk-cmdq: Add pa_base parsing for hardware without subsys ID support
  soc: mediatek: mtk-cmdq: Add cmdq_get_mbox_priv() in cmdq_pkt_create()
  mailbox: mtk-cmdq: Add driver data to support for MT8196
  mailbox: mtk-cmdq: Add mminfra_offset configuration for DRAM transaction
  ...
</content>
</entry>
<entry>
<title>Merge tag 'v7.0-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6</title>
<updated>2026-02-10T16:36:42Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-02-10T16:36:42Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=08df88fa142f3ba298bf0f7840fa9187e2fb5956'/>
<id>urn:sha1:08df88fa142f3ba298bf0f7840fa9187e2fb5956</id>
<content type='text'>
Pull crypto update from Herbert Xu:
 "API:
   - Fix race condition in hwrng core by using RCU

  Algorithms:
   - Allow authenc(sha224,rfc3686) in fips mode
   - Add test vectors for authenc(hmac(sha384),cbc(aes))
   - Add test vectors for authenc(hmac(sha224),cbc(aes))
   - Add test vectors for authenc(hmac(md5),cbc(des3_ede))
   - Add lz4 support in hisi_zip
   - Only allow clear key use during self-test in s390/{phmac,paes}

  Drivers:
   - Set rng quality to 900 in airoha
   - Add gcm(aes) support for AMD/Xilinx Versal device
   - Allow tfms to share device in hisilicon/trng"

* tag 'v7.0-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (100 commits)
  crypto: img-hash - Use unregister_ahashes in img_{un}register_algs
  crypto: testmgr - Add test vectors for authenc(hmac(md5),cbc(des3_ede))
  crypto: cesa - Simplify return statement in mv_cesa_dequeue_req_locked
  crypto: testmgr - Add test vectors for authenc(hmac(sha224),cbc(aes))
  crypto: testmgr - Add test vectors for authenc(hmac(sha384),cbc(aes))
  hwrng: core - use RCU and work_struct to fix race condition
  crypto: starfive - Fix memory leak in starfive_aes_aead_do_one_req()
  crypto: xilinx - Fix inconsistant indentation
  crypto: rng - Use unregister_rngs in register_rngs
  crypto: atmel - Use unregister_{aeads,ahashes,skciphers}
  hwrng: optee - simplify OP-TEE context match
  crypto: ccp - Add sysfs attribute for boot integrity
  dt-bindings: crypto: atmel,at91sam9g46-sha: add microchip,lan9691-sha
  dt-bindings: crypto: atmel,at91sam9g46-aes: add microchip,lan9691-aes
  dt-bindings: crypto: qcom,inline-crypto-engine: document the Milos ICE
  crypto: caam - fix netdev memory leak in dpaa2_caam_probe
  crypto: hisilicon/qm - increase wait time for mailbox
  crypto: hisilicon/qm - obtain the mailbox configuration at one time
  crypto: hisilicon/qm - remove unnecessary code in qm_mb_write()
  crypto: hisilicon/qm - move the barrier before writing to the mailbox register
  ...
</content>
</entry>
<entry>
<title>dt-bindings: crypto: inside-secure,safexcel: Mandate only ring IRQs</title>
<updated>2026-02-04T02:58:12Z</updated>
<author>
<name>AngeloGioacchino Del Regno</name>
<email>angelogioacchino.delregno@collabora.com</email>
</author>
<published>2026-01-12T14:55:56Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e2bafe4d1b72e6cd06ed9c0921cb3cce674db351'/>
<id>urn:sha1:e2bafe4d1b72e6cd06ed9c0921cb3cce674db351</id>
<content type='text'>
Not all IP implementations of EIP97 and EIP197 have the EIP and
MEM interrupts hooked up to the SoC, and those are not required
for functionality as status for both can be polled (and anyway
there's even no real need to poll, but that's another story).

As an example of this, the MediaTek MT7986A and MT7986B SoCs do
not have those two interrupts hooked up to their irq controlller.

For this reason, make the EIP and MEM interrupt optional on the
mediatek,mt7986-crypto.

Signed-off-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Link: https://patch.msgid.link/20260112145558.54644-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: crypto: inside-secure,safexcel: Add SoC compatibles</title>
<updated>2026-02-04T02:58:12Z</updated>
<author>
<name>AngeloGioacchino Del Regno</name>
<email>angelogioacchino.delregno@collabora.com</email>
</author>
<published>2026-01-12T14:55:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ad0cfd9985c5bbca63aba42685e6b9c0eb3cae61'/>
<id>urn:sha1:ad0cfd9985c5bbca63aba42685e6b9c0eb3cae61</id>
<content type='text'>
Add SoC specific compatibles for the SafeXcel crypto engine,
including one for the EIP197B used by Marvell Armada CP110 and
and two for the EIP97IES used by Marvell Armada 3700 and by
MediaTek MT7986.

Signed-off-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Link: https://patch.msgid.link/20260112145558.54644-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: crypto: atmel,at91sam9g46-sha: add microchip,lan9691-sha</title>
<updated>2026-01-31T02:56:47Z</updated>
<author>
<name>Robert Marko</name>
<email>robert.marko@sartura.hr</email>
</author>
<published>2026-01-15T11:37:30Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=64ae90a81aa4a5e51d0b4c2e836778ef40295651'/>
<id>urn:sha1:64ae90a81aa4a5e51d0b4c2e836778ef40295651</id>
<content type='text'>
Document Microchip LAN969x SHA compatible.

Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Acked-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>dt-bindings: crypto: atmel,at91sam9g46-aes: add microchip,lan9691-aes</title>
<updated>2026-01-31T02:56:47Z</updated>
<author>
<name>Robert Marko</name>
<email>robert.marko@sartura.hr</email>
</author>
<published>2026-01-15T11:37:29Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7f39ea40d4afc578bdd54b526fb1ba3ab2973c6a'/>
<id>urn:sha1:7f39ea40d4afc578bdd54b526fb1ba3ab2973c6a</id>
<content type='text'>
Document Microchip LAN969x AES compatible.

Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Acked-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@tuxon.dev&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
</feed>
