linux/Documentation/devicetree/bindings/dma, branch master

dt-bindings: dmaengine: Fix spelling mistake "Looongson" -> "Looogson"

2026-03-18T09:41:15Z

There is a spelling mistake in the title field. Fix it. Signed-off-by: Colin Ian King Reviewed-by: Binbin Zhou Link: https://patch.msgid.link/20260317204938.120729-1-colin.i.king@gmail.com Signed-off-by: Vinod Koul

dt-bindings: dmaengine: Add Loongson Multi-Channel DMA controller

2026-03-17T11:18:55Z

The Loongson-2K0300/Loongson-2K3000 have built-in multi-channel DMA controllers, which are similar except for some of the register offsets and number of channels. Obviously, this is quite different from the APB DMA controller used in the Loongson-2K0500/Loongson-2K1000, such as the latter being a single-channel DMA controller. To avoid cluttering a single dt-binding file, add a new yaml file. Reviewed-by: Rob Herring (Arm) Signed-off-by: Binbin Zhou Reviewed-by: Huacai Chen Link: https://patch.msgid.link/135802de72b84f643d0b0624f3f79f13777147a1.1772853681.git.zhoubinbin@loongson.cn Signed-off-by: Vinod Koul

dt-bindings: dma: xlnx,axi-dma: Convert to DT schema

2026-03-17T10:56:24Z

Convert the bindings document for Xilinx DMA. No changes to existing binding description. Signed-off-by: Abin Joseph Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260309033444.3472359-1-abin.joseph@amd.com Signed-off-by: Vinod Koul

dt-bindings: dma: rz-dmac: Add conditional schema for RZ/G3L

2026-03-17T10:55:56Z

The RZ/G3L DMA controller is compatible with RZ/G2L, sharing the same IP. However, the conditional schema logic that enforces RZ/G2L-specific binding constraints was not extended to cover the RZ/G3L compatible string, leaving its bindings without proper validation. Add the RZ/G3L compatible string to the existing RZ/G2L conditional schema so that the same property constraints are applied to both SoCs. Signed-off-by: Biju Das Fixes: e45cf0c7d9b960f1 ("dt-bindings: dma: rz-dmac: Document RZ/G3L SoC") Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260306145819.897047-1-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul

dt-bindings: dma: renesas,rz-dmac: document RZ/{T2H,N2H}

2026-03-09T11:26:30Z

The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have three DMAC instances. Compared to the previously supported RZ/V2H, these SoCs are missing the error interrupt line and the reset lines, and they use a different ICU IP. Document them, and use RZ/T2H as a fallback for RZ/N2H as the DMACs are entirely compatible. Signed-off-by: Cosmin Tanislav Reviewed-by: Rob Herring (Arm) Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260105114445.878262-4-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Vinod Koul

dt-bindings: dma: snps,dw-axi-dmac: Add CV1800B compatible

2026-02-26T15:30:01Z

The DMA controller on CV1800B needs to use the DMA phandle args as the channel number instead of hardware handshake number, so add a new compatible for the DMA controller on CV1800B. Signed-off-by: Inochi Amaoto Acked-by: Conor Dooley Link: https://patch.msgid.link/20260120013706.436742-2-inochiama@gmail.com Signed-off-by: Vinod Koul

dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property

2026-02-25T09:59:53Z

The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller operates on a cache-coherent AXI interface, where DMA transactions are automatically kept coherent with the CPU caches. In previous generations SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there is no need for dma-coherent property to be presence. In Agilex 5, the architecture has changed. It introduced a coherent interconnect that supports cache-coherent DMA. Signed-off-by: Khairul Anuar Romli Reviewed-by: Rob Herring (Arm) Signed-off-by: Dinh Nguyen Link: https://patch.msgid.link/20260131172856.29227-1-dinguyen@kernel.org Signed-off-by: Vinod Koul

dt-bindings: dma: rz-dmac: Document RZ/G3L SoC

2026-02-25T09:58:56Z

Document the Renesas RZ/G3L DMAC block. This is identical to the one found on the RZ/G3S SoC. Reviewed-by: Fabrizio Castro Acked-by: Conor Dooley Signed-off-by: Biju Das Link: https://patch.msgid.link/20260203103031.247435-2-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul

Merge tag 'dmaengine-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine

2026-02-17T19:47:17Z

Pull dmaengine updates from Vinod Koul: "Core: - Add Frank Li as susbstem reviewer to help with reviews New Support: - Mediatek support for Dimensity 6300 and 9200 controller - Qualcomm Kaanapali and Glymur GPI DMA engine - Synopsis DW AXI Agilex5 - Renesas RZ/V2N SoC - Atmel microchip lan9691-dma - Tegra ADMA tegra264 Updates: - sg_nents_for_dma() helper use in subsystem - pm_runtime_mark_last_busy() redundant call update for subsystem - Residue support for xilinx AXIDMA driver - Intel Max SGL Size Support and capabilities for DSA3.0 - AXI dma larger than 32bits address support" * tag 'dmaengine-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (64 commits) dmaengine: add Frank Li as reviewer dt-bindings: dma: qcom,gpi: Update max interrupts lines to 16 dmaengine: fsl-edma: don't explicitly disable clocks in .remove() dmaengine: xilinx: xdma: use sg_nents_for_dma() helper dmaengine: sh: use sg_nents_for_dma() helper dmaengine: sa11x0: use sg_nents_for_dma() helper dmaengine: qcom: bam_dma: use sg_nents_for_dma() helper dmaengine: qcom: adm: use sg_nents_for_dma() helper dmaengine: pxa-dma: use sg_nents_for_dma() helper dmaengine: lgm: use sg_nents_for_dma() helper dmaengine: k3dma: use sg_nents_for_dma() helper dmaengine: dw-axi-dmac: use sg_nents_for_dma() helper dmaengine: bcm2835-dma: use sg_nents_for_dma() helper dmaengine: axi-dmac: use sg_nents_for_dma() helper dmaengine: altera-msgdma: use sg_nents_for_dma() helper scatterlist: introduce sg_nents_for_dma() helper dmaengine: idxd: Add Max SGL Size Support for DSA3.0 dmaengine: idxd: Expose DSA3.0 capabilities through sysfs dmaengine: sh: rz-dmac: Make channel irq local dmaengine: pl08x: Fix comment stating the difference between PL080 and PL081 ...

dt-bindings: dma: qcom,gpi: Update max interrupts lines to 16

2026-02-04T16:58:38Z

Update interrupt maxItems to 16 from 13 per GPI instance to support Glymur, Qualcomm's latest gen SoC Signed-off-by: Pankaj Patil Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251231133114.2752822-1-pankaj.patil@oss.qualcomm.com Signed-off-by: Vinod Koul