linux/Documentation/devicetree/bindings/rtc, branch v6.17

Merge tag 'rtc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux

2025-08-04T03:17:34Z

Pull RTC updates from Alexandre Belloni: "Support for a new RTC in an existing driver and all the drivers exposing clocks using the common clock framework have been converted to determine_rate(). Summary: Subsystem: - Convert drivers exposing a clock from round_rate() to determine_rate() Drivers: - ds1307: oscillator stop flag handling for ds1341 - pcf85063: add support for RV8063" * tag 'rtc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: (34 commits) rtc: ds1685: Update Joshua Kinard's email address. rtc: rv3032: convert from round_rate() to determine_rate() rtc: rv3028: convert from round_rate() to determine_rate() rtc: pcf8563: convert from round_rate() to determine_rate() rtc: pcf85063: convert from round_rate() to determine_rate() rtc: nct3018y: convert from round_rate() to determine_rate() rtc: max31335: convert from round_rate() to determine_rate() rtc: m41t80: convert from round_rate() to determine_rate() rtc: hym8563: convert from round_rate() to determine_rate() rtc: ds1307: convert from round_rate() to determine_rate() rtc: rv3028: fix incorrect maximum clock rate handling rtc: pcf8563: fix incorrect maximum clock rate handling rtc: pcf85063: fix incorrect maximum clock rate handling rtc: nct3018y: fix incorrect maximum clock rate handling rtc: hym8563: fix incorrect maximum clock rate handling rtc: ds1307: fix incorrect maximum clock rate handling rtc: pcf85063: scope pcf85063_config structures rtc: Optimize calculations in rtc_time64_to_tm() dt-bindings: rtc: amlogic,a4-rtc: Add compatible string for C3 rtc: ds1307: handle oscillator stop flag (OSF) for ds1341 ...

Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2025-07-29T18:04:52Z

Pull SoC devicetree updates from Arnd Bergmann: "There are a few new variants of existing chips: - mt6572 is an older mobile phone chip from mediatek that was extremely popular a decade ago but never got upstreamed until now - exynos2200 is a recent high-end mobile phone chip used in a few Samsung phones like the Galaxy S22 - Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M (R8A779H0) and used in automotive applications - Tegra264 is a new chip from NVIDIA, but support is fairly minimal for now, and not much information is public about it There are five more chips in a separate branch, as those are new chip families that I merged along with the necessary infrastructure. New board support is not that exciting, with a total of 33 newly added machines here: - Evaluation platforms for the chips above, plus TI am62d2 and Sophgo sg2042 - Six 32-bit industrial boards based on stm32, imx6 and am33 chips, plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and imx95 - Two newly added ASPEED BMC based motherboards, and one that got removed - Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit msm8976 SoCs - Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1 - A set-top box based on Amlogic meson-gxm Updates for existing machines are spread over all the above families. One notable change here is support for the RP1 I/O chip used in Raspberry Pi 5" * tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (606 commits) riscv: dts: sophgo: fix mdio node name for CV180X riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings riscv: dts: sophgo: add ethernet GMAC device for sg2042 riscv: dts: sophgo: Enable ethernet device for Huashan Pi riscv: dts: sophgo: Add mdio multiplexer device for cv18xx riscv: dts: sophgo: Add ethernet device for cv18xx riscv: dts: sophgo: sg2044: add pmu configuration riscv: dts: sophgo: sg2044: add ziccrse extension riscv: dts: sophgo: add zfh for sg2042 riscv: dts: sophgo: add ziccrse for sg2042 riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree riscv: dts: sophgo: sg2044: add PCIe device support for SG2044 riscv: dts: sophgo: sg2044: add MSI device support for SG2044 riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property ...

dt-bindings: Correct indentation and style in DTS example

2025-07-29T00:56:29Z

DTS example in the bindings should be indented with 2- or 4-spaces and aligned with opening '- |', so correct any differences like 3-spaces or mixtures 2- and 4-spaces in one binding. No functional changes here, but saves some comments during reviews of new patches built on existing code. Acked-by: Ulf Hansson # For MMC Acked-by: Lee Jones Acked-by: Thierry Reding Reviewed-by: Geert Uytterhoeven # renesas Link: https://lore.kernel.org/r/20250107131456.247610-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250725100241.120106-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm)

dt-bindings: rtc: amlogic,a4-rtc: Add compatible string for C3

2025-07-23T21:43:44Z

Amlogic C3 SoCs uses the same rtc controller as A5 SoCs. There is no need for an extra compatible line in the driver, but add C3 compatible line for documentation. Signed-off-by: Xianwei Zhao Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250717-rtc-c3-node-v1-1-4f9ae059b8e6@amlogic.com Signed-off-by: Alexandre Belloni

dt-bindings: rtc: pcf85063: add binding for RV8063

2025-07-23T16:52:08Z

Microcrystal RV8063 is a real-time clock module with SPI interface. Reviewed-by: Rob Herring (Arm) Signed-off-by: Antoni Pokusinski Link: https://lore.kernel.org/r/20250413130755.159373-2-apokusinski01@gmail.com Signed-off-by: Alexandre Belloni

dt-bindings: rtc: tegra: Document Tegra264 RTC

2025-07-11T14:48:07Z

Add the compatible string for the RTC block found on the Tegra264 SoC. Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250507143802.1230919-3-thierry.reding@gmail.com Signed-off-by: Thierry Reding

dt-bindings: rtc: nxp,lpc1788-rtc: add compatible string nxp,lpc1850-rtc

2025-07-07T21:42:15Z

Add compatible string nxp,lpc1850-rtc and fallback to nxp,lpc1788-rtc. Fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: rtc@40046000 (nxp,lpc1850-rtc): compatible: ['nxp,lpc1850-rtc', 'nxp,lpc1788-rtc'] is too long Signed-off-by: Frank Li Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250602142842.942700-1-Frank.Li@nxp.com Signed-off-by: Alexandre Belloni

dt-bindings: rtc: move nxp,lpc3220-rtc to separated file from trivial-rtc.yaml

2025-07-07T21:42:00Z

nxp,lpc3220-rtc have clocks property, so move it from trivial-rtc.yaml. Signed-off-by: Frank Li Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250624201733.2515971-1-Frank.Li@nxp.com Signed-off-by: Alexandre Belloni

dt-bindings: Move sophgo,cv1800b-rtc to rtc directory

2025-07-07T21:41:38Z

The $id path for the sophgo,cv1800b-rtc binding was missing part of the path 'soc'. However, the correct place for RTC bindings (even if it's also a "syscon") is the rtc directory, so move the binding there while fixing the $id value. Fixes: 76517429dbfd ("dt-bindings: soc: sophgo: add RTC support for Sophgo CV1800 series") Signed-off-by: Rob Herring (Arm) Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250608224252.3902421-1-robh@kernel.org Signed-off-by: Alexandre Belloni

dt-bindings: rtc: rzn1: add optional second clock

2025-06-01T21:53:02Z

The external crystal can be a second clock input. It is needed for the SCMP counting method which allows using crystals different than 32768Hz. It is also needed for an upcoming SoC which only supports the SCMP method. Signed-off-by: Wolfram Sang Reviewed-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20250526095801.35781-6-wsa+renesas@sang-engineering.com Signed-off-by: Alexandre Belloni