linux/Documentation/devicetree/bindings/timer, branch v4.0

Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2015-02-16T23:26:10Z

Pull clocksource updates from Ingo Molnar: "The main change in this tree is the addition of various new SoC clocksource/clockevents drivers: Conexant Digicolor SoCs, rockchip rk3288 board, asm9260 for MIPS and versatile AB/PB boards" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: dts: versatile: Add sysregs node clocksource: versatile: Adapt for Versatile AB and PB boards dt/bindings: Add binding for Versatile system registers clocksource: Driver for Conexant Digicolor SoC timer clocksource: devicetree: Document Conexant Digicolor timer binding clockevents: rockchip: Add rockchip timer for rk3288 ARM: clocksource: Add asm9260_timer driver clocksource: marco: Rename marco to atlas7 clocksource: sirf: Remove unused variable

Documentation: DT bindings: add more Tegra chip compatible strings

2015-02-04T02:37:31Z

Align compatible strings for several IP blocks present on Tegra chips with the latest doctrine from the DT maintainers: http://marc.info/?l=devicetree&m=142255654213019&w=2 The primary objective here is to avoid checkpatch warnings, per: http://marc.info/?l=linux-tegra&m=142201349727836&w=2 DT binding text files have been updated for the following IP blocks: - PCIe - SOR - SoC timers - AHB "gizmo" - APB_MISC - pinmux control - UART - PWM - I2C - SPI - RTC - PMC - eFuse - AHCI - HDA - XUSB_PADCTRL - SDHCI - SOC_THERM - AHUB - I2S - EHCI - USB PHY N.B. The nvidia,tegra20-timer compatible string is removed from the nvidia,tegra30-timer.txt documentation file because it's already mentioned in the nvidia,tegra20-timer.txt documentation file. This second version takes into account the following requests from Rob Herring : - Per-IP block patches have been combined into a single patch - Explicit documentation about which compatible strings are actually matched by the driver has been removed. In its place is implicit documentation that loosely follows Rob's prescribed format: "Must contain '"nvidia,-pcie", "nvidia,tegra20-pcie"' where is tegra30, tegra132, ..." [...] "You should attempt to document known values of if you use it" Signed-off-by: Paul Walmsley Cc: Alexandre Courbot Cc: Dylan Reid Cc: Greg Kroah-Hartman Cc: Hans de Goede Cc: Ian Campbell Cc: Jingchang Lu Cc: John Crispin Cc: Kumar Gala Cc: Linus Walleij Cc: Mark Rutland Cc: Mikko Perttunen Cc: Murali Karicheri Cc: Paul Walmsley Cc: Pawel Moll Cc: Peter De Schrijver Cc: Peter Hurley Cc: Sean Paul Cc: Stephen Warren Cc: Takashi Iwai Cc: Tejun Heo Cc: "Terje Bergström" Cc: Thierry Reding Cc: Tuomas Tynkkynen Cc: Wolfram Sang Cc: Zhang Rui Cc: dri-devel@lists.freedesktop.org Cc: linux-i2c@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-pwm@vger.kernel.org Cc: linux-tegra@vger.kernel.org Acked-by: Eduardo Valentin Signed-off-by: Rob Herring

clocksource: devicetree: Document Conexant Digicolor timer binding

2015-01-29T13:02:14Z

The Conexant CX92755 SoC provides 8 32-bit timers as part of its so called "Agent Communication" block. Timers can be configures either as free running or one shot. Each timer has a dedicated interrupt source in the CX92755 interrupts controller. The first timer (Timer A) can also be configured as watchdog. This commit adds devicetree binding definition of this hardware module. The binding defined here should be reusable for other SoCs in the Digicolor series. Signed-off-by: Baruch Siach Signed-off-by: Daniel Lezcano

clockevents: rockchip: Add rockchip timer for rk3288

2015-01-29T13:02:13Z

The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano Reviewed-by: Heiko Stuebner

Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2014-12-10T16:18:32Z

Pull timer core updates from Thomas Gleixner: "The time(r) departement provides: - more infrastructure work on the year 2038 issue - a few fixes in the Armada SoC timers - the usual pile of fixlets and improvements" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: clocksource: armada-370-xp: Use the reference clock on A375 SoC watchdog: orion: Use the reference clock on Armada 375 SoC clocksource: armada-370-xp: Add missing clock enable time: Fix sign bug in NTP mult overflow warning time: Remove timekeeping_inject_sleeptime() rtc: Update suspend/resume timing to use 64bit time rtc/lib: Provide y2038 safe rtc_tm_to_time()/rtc_time_to_tm() replacement time: Fixup comments to reflect usage of timespec64 time: Expose get_monotonic_coarse64() for in-kernel uses time: Expose getrawmonotonic64 for in-kernel uses time: Provide y2038 safe mktime() replacement time: Provide y2038 safe timekeeping_inject_sleeptime() replacement time: Provide y2038 safe do_settimeofday() replacement time: Complete NTP adjustment threshold judging conditions time: Avoid possible NTP adjustment mult overflow. time: Rename udelay_test.c to test_udelay.c clocksource: sirf: Remove hard-coded clock rate

clocksource: armada-370-xp: Use the reference clock on A375 SoC

2014-11-26T12:51:08Z

The 25 MHz reference clock has better stability so its use is preferred over the core clock. This commit takes advantage of the already introduced Armada 375 devicetree compatible string and adds a new timer initialization. If available, the timer will use the reference clock (named as 'fixed'). Otherwise, it falls back to the previous behavior. Acked-by: Jason Cooper Acked-by: Gregory CLEMENT Acked-by: Wim Van Sebroeck Reviewed-by: Thomas Petazzoni Tested-by: Thomas Petazzoni Signed-off-by: Ezequiel Garcia Signed-off-by: Daniel Lezcano

clocksource: sh_mtu2: Drop incorrect SoC family name

2014-10-27T01:00:36Z

The MTU2 hardware block is found in many Renesas SH and ARM SoCs, but not in R-Car. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman

clocksource: sh_tmu: Document r8a7778 binding

2014-10-27T01:00:36Z

The r8a7778 is very similar to the r8a7779, and already handled by the current driver in the non-DT case. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman

clocksource: sh_tmu: Document R-Mobile r8a7740 binding

2014-10-27T01:00:35Z

Compared to the r8a7779, the r8a7740 lacks the input capture register, which is not used by the driver (the current driver already handles the r8a7740 in the non-DT case). Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman

Merge tag 'renesas-clocksource-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into clockevents/3.18

2014-09-28T23:59:51Z

Renesas Clocksource Updates for v3.18 * Document per-SoC bindings Signed-off-by: Daniel Lezcano