linux/arch/arc/kernel/entry-compact.S, branch v4.9

ARC: [intc-compact] simplify code for 2 priority levels

2016-05-30T17:15:04Z

ARC700 support for 2 interrupt priorities historically allowed even slow perpherals such as emac and uart to setup high priority interrupts which was wrong from the beginning as they could possibly delay the more critical timer interrupt. The hardware support for 2 level interrupts in ARCompact is less than ideal anyways (judging from the "hacks" in low level entry code and thus is not used in productions systems I know of. So reduce the scope of this to timer only, thereby reducing a bunch of complexity. Signed-off-by: Vineet Gupta

ARCv2: Enable LOCKDEP

2016-04-22T12:42:31Z

- The asm helpers for calling into irq tracer were missing - Add calls to above helpers in low level assembly entry code for ARCv2 - irq_save() uses CLRI to disable interrupts and returns the prev interrupt state (in STATUS32) in a specific encoding (and not the raw value of STATUS32). This is usable with SETI in irq_restore(). However save_flags() reads the raw value of STATUS32 which doesn't pair with irq_save/restore() and thus needs fixing. Signed-off-by: Evgeny Voevodin [vgupta: updated changelog and also added some comments] Signed-off-by: Vineet Gupta

ARC: [arcompact] Handle bus error from userspace as Interrupt not exception

2015-11-14T07:42:20Z

Bus errors from userspace on ARCompact based cores are handled by core as a high priority L2 interrupt but current code treated it as interrupt Handling an interrupt like exception is certainly not going to go unnoticed. (and it worked so far as we never saw a Bus error from userspace until IPPK guys tested a DDR controller with ECC error detection etc hence needed to explicitly trigger/handle such errors) - So move mem_service exception handler from common code into ARCv2 code. - In ARCompact code, define mem_service as L2 interrupt handler which just drops down to pure kernel mode and goes of to enqueue SIGBUS Reported-by: Nelson Pereira Tested-by: Ana Martins Signed-off-by: Vineet Gupta

ARC: boot: Support Halt-on-reset and Run-on-reset SMP booting modes

2015-10-28T10:38:17Z

For Run-on-reset, non masters need to spin wait. For Halt-on-reset they can jump to entry point directly. Also while at it, made reset vector handler as "the" entry point for kernel including host debugger based boot (which uses the ELF header entry point) Signed-off-by: Vineet Gupta

ARC: [arcompact] entry.S: Elide extra check/branch in exception ret path

2015-10-17T12:18:23Z

This is done by improving the laddering logic ! Before: if Exception goto excep_or_pure_k_ret if !Interrupt(L2) goto l1_chk else INTERRUPT_EPILOGUE 2 l1_chk: if !Interrupt(L1) (i.e. pure kernel mode) goto excep_or_pure_k_ret else INTERRUPT_EPILOGUE 1 excep_or_pure_k_ret: EXCEPTION_EPILOGUE Now: if !Interrupt(L1 or L2) (i.e. exception or pure kernel mode) goto excep_or_pure_k_ret ; guaranteed to be an interrupt if !Interrupt(L2) goto l1_ret else INTERRUPT_EPILOGUE 2 ; by virtue of above, no need to chk for L1 active l1_ret: INTERRUPT_EPILOGUE 1 excep_or_pure_k_ret: EXCEPTION_EPILOGUE Signed-off-by: Vineet Gupta

ARC: [arcompact] entry.S: Document preemption games for L2 intr

2015-10-17T12:18:23Z

Signed-off-by: Vineet Gupta

ARC: entry.S: use single EXCEPTION_PROLOGUE

2015-06-19T12:39:39Z

Returning from pure kernel mode and exception mode use the same code anyways. Remove one the duplicate blocks Signed-off-by: Vineet Gupta

ARC: entry.S: move some code around for cache locality in return path

2015-06-19T12:39:38Z

Signed-off-by: Vineet Gupta

ARC: entry.S: split into ARCompact ISA specific, common bits

2015-06-19T12:39:38Z

Signed-off-by: Vineet Gupta