linux/arch/arc/kernel/entry.S, branch v3.12

ARC: Entry Handler tweaks: Optimize away redundant IRQ_DISABLE_SAVE

2013-08-26T04:10:25Z

In the exception return path, for both U/K cases, intr are already disabled (for various existing reasons). So when we drop down to @restore_regs, we need not redo that. There was subtle issue - when intr were NOT being disabled for ret-to-kernel-but-no-preemption case - now fixed by moving the IRQ_DISABLE further up in @resume_kernel_mode. So what do we gain: * Shaves off a few insn in return path. * Eliminates the need for IRQ_DISABLE_SAVE assembler macro for ARCv2 hence allows for entry code sharing. Signed-off-by: Vineet Gupta

ARC: Exception Handlers Code consolidation

2013-08-26T04:10:25Z

After the recent cleanups, all the exception handlers now have same boilerplate prologue code. Move that into common macro. This reduces readability but helps greatly with sharing / duplicating entry code with ARCv2 ISA where the handlers are pretty much the same, just the entry prologue is different (due to hardware assist). Also while at it, add the missing FAKE_RET_FROM_EXCPN calls in couple of places to drop down to pure kernel mode (from exception mode) before jumping off into "C" code. Signed-off-by: Vineet Gupta

ARC: Remove explicit passing around of ECR

2013-06-26T10:00:50Z

With ECR now part of pt_regs * No need to propagate from lowest asm handlers as arg * No need to save it in tsk->thread.cause_code * Avoid bit chopping to access the bit-fields More code consolidation, cleanup Signed-off-by: Vineet Gupta

ARC: pt_regs update #5: Use real ECR for pt_regs->event vs. synth values

2013-06-26T08:34:48Z

pt_regs->event was set with artificial values to identify the low level system event (syscall trap / breakpoint trap / exceptions / interrupts) With r8 saving out of the way, the full word can be used to save real ECR (Exception Cause Register) which helps idenify the event naturally, including additional info such as cause code, param. Only for Interrupts, where ECR is not applicable, do we resort to synthetic non ECR values. SAVE_ALL_TRAP/EXCEPTIONS can now be merged as they both use ECR with different runtime values. The ptrace helpers now use the sub-fields of ECR to distinguish the events (e.g. vector 0x25 is trap, param 0 is syscall...) The following benefits will follow: (1) This centralizes the location of where ECR is saved and will allow the cleanup of task->thread.cause_code ECR placeholder which is set in non-uniform way. Then ARC VM code can safely rely on it being there for purpose of finer grained VM_EXEC dcache flush (based on exec fault: I-TLB Miss) (2) Further, ECR being passed around from low level handlers as arg can be eliminated as it is part of standard reg-file in pt_regs Signed-off-by: Vineet Gupta

ARC: pt_regs update #4: r25 saved/restored unconditionally

2013-06-22T13:53:25Z

(This is a VERY IMP change for low level interrupt/exception handling) ----------------------------------------------------------------------- WHAT ----------------------------------------------------------------------- * User 25 now saved in pt_regs->user_r25 (vs. tsk->thread_info.user_r25) * This allows Low level interrupt code to unconditionally save r25 (vs. the prev version which would only do it for U->K transition). Ofcourse for nested interrupts, only the pt_regs->user_r25 of bottom-most frame is useful. * simplifies the interrupt prologue/epilogue * Needed for ARCv2 ISA code and done here to keep design similar with ARCompact event handling ----------------------------------------------------------------------- WHY ------------------------------------------------------------------------- With CONFIG_ARC_CURR_IN_REG, r25 is used to cache "current" task pointer in kernel mode. So when entering kernel mode from User Mode - user r25 is specially safe-kept (it being a callee reg is NOT part of pt_regs which are saved by default on each interrupt/trap/exception) - r25 loaded with current task pointer. Further, if interrupt was taken in kernel mode, this is skipped since we know that r25 already has valid "current" pointer. With 2 level of interrupts in ARCompact ISA, detecting this is difficult but still possible, since we could be in kernel mode but r25 not already saved (in fact the stack itself might not have been switched). A. User mode B. L1 IRQ taken C. L2 IRQ taken (while on 1st line of L1 ISR) So in #C, although in kernel mode, r25 not saved (infact SP not switched at all) Given that ARcompact has manual stack switching, we could use a bit of trickey - The low level code would make sure that SP is only set to kernel mode value at the very end (after saving r25). So a non kernel mode SP, even if in kernel mode, meant r25 was NOT saved. The same paradigm won't work in ARCv2 ISA since SP is auto-switched so it's setting can't be delayed/constrained. Signed-off-by: Vineet Gupta

ARC: Entry Handler tweaks: Simplify branch for in-kernel preemption

2013-06-22T13:53:24Z

Signed-off-by: Vineet Gupta

ARC: Entry Handler tweaks: Avoid hardcoded LIMMS for ECR values

2013-06-22T13:53:23Z

Signed-off-by: Vineet Gupta

ARC: [mm] Remove @write argument to do_page_fault()

2013-06-22T13:53:20Z

This can be ascertained within do_page_fault() since it gets the full ECR (Exception Cause Register). Further, for both the callers of do_page_fault(): Prot-V / D-TLB-Miss, the cause sub-fields in ECR are same for same type of access, making the code much more simpler. D-TLB-Miss [LD] 0x00_21_01_00 Prot-V [LD] 0x00_23_01_00 ^^ D-TLB-Miss [ST] 0x00_21_02_00 Prot-V [ST] 0x00_23_02_00 ^^ D-TLB-Miss [EX] 0x00_21_03_00 Prot-V [EX] 0x00_23_03_00 ^^ This helps code consolidation, which is even better when moving code from assembler to "C". Signed-off-by: Vineet Gupta

ARC: unaligned access emulation broken if callee-reg dest of LD/ST

2013-05-07T08:13:55Z

The fixup code correctly updates the callee-regs on stack, but fails to unwind it into actual register file. Thus userspace won't see the update. Reported-by: Noam Camus Signed-off-by: Vineet Gupta

ARC: unaligned access emulation error handling consolidation

2013-05-07T08:13:55Z

If CONFIG_ARC_MISALIGN_ACCESS is not enabled, or if the fixup fails, call the same error handler: same signal/si_code to user (SIGBUS) Signed-off-by: Vineet Gupta