linux/arch/arc/kernel/entry.S, branch v3.9

ARC: Fix the typo in event identifier flags used by ptrace

2013-03-20T13:15:45Z

orig_r8_IS_EXCPN and orig_r8_IS_BRKPT were same values due to a copy/paste error. Although it looks bad and is wrong, it really doesn't affect gdb working. orig_r8_IS_BRKPT is the one relevant to debugging (breakpoints), since it is used to provide EFA vs. ERET to a ptrace "stop_pc" request. So when gdb has inserted a breakpoint, orig_r8_IS_BRKPT is already set, and anything else (i.e. orig_r8_IS_EXCPN) becoming same as it, really doesn't hurt gdb. The corollary case, could be nasty but nobody uses the ptrace "stop_pc" request in that case Signed-off-by: Vineet Gupta

ARC: ABIv3: fork/vfork wrappers not needed in "no-legacy-syscall" ABI

2013-03-11T13:31:10Z

When switching to clone() only ABI - I missed out pruning the low level asm syscall wrappers Signed-off-by: Vineet Gupta

ARC: Fix pt_orig_r8 access

2013-02-15T17:46:21Z

Syscall restarting fixes made pt_regs->orig_r8 a short word, which was not reflected in the assembler code - thus could potentially break gdb debugging. Signed-off-by: Vineet Gupta

ARC: Support for single cycle Close Coupled Mem (CCM)

2013-02-15T17:46:10Z

* Includes mapping of CCMs in address space * Annotations to move arbitrary code/data into CCM * Moving some of the critical code/data into CCM * Runtime detection/reporting Signed-off-by: Vineet Gupta

ARC: Unaligned access emulation

2013-02-15T17:46:06Z

ARC700 doesn't natively support unaligned access, but can be emulated -Unaligned Access Exception -Disassembly at the Fault address to find the exact insn (long/short) Also per Arnd's comment, we runtime control it using 2 sysctl knobs: * SYSCTL_ARCH_UNALIGN_ALLOW: Runtime enable/disble * SYSCTL_ARCH_UNALIGN_NO_WARN: Warn on each emulation attempt Originally contributed by Tim Yao Signed-off-by: Vineet Gupta Cc: Tim Yao Acked-by: Arnd Bergmann

ARC: DWARF2 .debug_frame based stack unwinder

2013-02-15T17:46:03Z

-Originally written by Rajeshwar Ranga -Derived off of generic unwinder in 2.6.19 and adapted to ARC Signed-off-by: Vineet Gupta Cc: Rajeshwar Ranga

ARC: SMP support

2013-02-15T17:46:02Z

ARC common code to enable a SMP system + ISS provided SMP extensions. ARC700 natively lacks SMP support, hence some of the core features are are only enabled if SoCs have the necessary h/w pixie-dust. This includes: -Inter Processor Interrupts (IPI) -Cache coherency -load-locked/store-conditional ... The low level exception handling would be completely broken in SMP because we don't have hardware assisted stack switching. Thus a fair bit of this code is repurposing the MMU_SCRATCH reg for event handler prologues to keep them re-entrant. Many thanks to Rajeshwar Ranga for his initial "major" contributions to SMP Port (back in 2008), and to Noam Camus and Gilad Ben-Yossef for help with resurrecting that in 3.2 kernel (2012). Note that this platform code is again singleton design pattern - so multiple SMP platforms won't build at the moment - this deficiency is addressed in subsequent patches within this series. Signed-off-by: Vineet Gupta Cc: Arnd Bergmann Cc: Thomas Gleixner Cc: Rajeshwar Ranga Cc: Noam Camus Cc: Gilad Ben-Yossef

ARC: Support for high priority interrupts in the in-core intc

2013-02-15T17:46:01Z

There is a bit of hack/kludge right now where we disable preemption if a L2 (High prio) IRQ is taken while L1 (Low prio) is active. Need to revisit this Signed-off-by: Vineet Gupta

ARC: ptrace support

2013-02-15T17:45:59Z

Signed-off-by: Vineet Gupta Acked-by: Arnd Bergmann

ARC: [optim] Cache "current" in Register r25

2013-02-15T17:45:58Z

Signed-off-by: Vineet Gupta