linux/arch/arc/kernel/setup.c, branch v4.3

ARCv2: spinlock/rwlock/atomics: Delayed retry of failed SCOND with exponential backoff

2015-08-04T03:56:34Z

This is to workaround the llock/scond livelock HS38x4 could get into a LLOCK/SCOND livelock in case of multiple overlapping coherency transactions in the SCU. The exclusive line state keeps rotating among contenting cores leading to a never ending cycle. So break the cycle by deferring the retry of failed exclusive access (SCOND). The actual delay needed is function of number of contending cores as well as the unrelated coherency traffic from other cores. To keep the code simple, start off with small delay of 1 which would suffice most cases and in case of contention double the delay. Eventually the delay is sufficient such that the coherency pipeline is drained, thus a subsequent exclusive access would succeed. Link: http://lkml.kernel.org/r/1438612568-28265-1-git-send-email-vgupta@synopsys.com Acked-by: Peter Zijlstra (Intel) Signed-off-by: Vineet Gupta

ARCv2: Fix the peripheral address space detection

2015-08-03T14:04:07Z

With HS 2.1 release, the peripheral space register no longer contains the uncached space specifics, causing the kernel to panic early on. So read the newer NON VOLATILE AUX register to get that info. Signed-off-by: Vineet Gupta

ARCv2: support HS38 releases

2015-07-13T08:03:23Z

Signed-off-by: Vineet Gupta

ARC: slightly refactor macros for boot logging

2015-07-09T12:06:33Z

Signed-off-by: Vineet Gupta

ARCv2: clocksource: Introduce 64bit local RTC counter

2015-06-22T08:36:56Z

Cc: Daniel Lezcano Cc: Thomas Gleixner Signed-off-by: Vineet Gupta

ARCv2: STAR 9000793984: Handle return from intr to Delay Slot

2015-06-22T08:36:55Z

Signed-off-by: Vineet Gupta

ARCv2: Support for ARCv2 ISA and HS38x cores

2015-06-22T08:36:55Z

The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta

ARC: uncached base is hard constant for ARC, don't save it

2015-06-22T08:36:54Z

ioremap already uses the hard define, just make sure BCR value matches that Signed-off-by: Vineet Gupta

ARC: explicit'ify uboot support

2015-06-19T12:39:27Z

Signed-off-by: Vineet Gupta

ARC: RIP broken 64bit RTSC

2015-06-19T12:39:24Z

Signed-off-by: Vineet Gupta