linux/arch/arc/kernel/setup.c, branch v4.5

ARCv2: boot report CCMs (Closely Coupled Memories)

2016-02-18T12:00:18Z

- ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta

ARC: Assume multiplier is always present

2016-02-18T12:00:03Z

It is unlikely that designs running Linux will not have multiplier. Further the current support is not complete as tool don't generate a multilib w/o multiplier. Signed-off-by: Vineet Gupta

ARCv2: Check for LL-SC livelock only if LLSC is enabled

2016-01-29T11:21:04Z

Signed-off-by: Vineet Gupta

ARC: shrink cpuinfo by not saving full timer BCR

2016-01-29T11:21:03Z

Signed-off-by: Vineet Gupta

ARC: dw2 unwind: Reinstante unwinding out of modules

2015-12-17T05:40:23Z

The fix which removed linear searching of dwarf (because binary lookup data always exists) missed out on the fact that modules don't get the binary lookup tables info. This caused unwinding out of modules to stop working. So add binary lookup header setup (equivalent of eh_frame_hdr setup) to modules as well. While at it, confine the header setup to within unwinder code, reducing one API exposed out of unwinder code. Fixes: 2e22502c080f ARC: dw2 unwind: Remove falllback linear search thru FDE entries Cc: Signed-off-by: Vineet Gupta

ARC: smp: Introduce smp hook @init_early_smp for Master core

2015-10-28T10:43:40Z

This adds a platform agnostic early SMP init hook which is called on Master core before calling setup_processor() setup_arch() smp_init_cpus() smp_ops.init_early_smp() ... setup_processor() How this helps: - Used for one time init of certain SMP centric IP blocks, before calling setup_processor() which probes various bits of core, possibly including this block - Currently platforms need to call this IP block init from their init routines, which doesn't make sense as this is specific to ARC core and not platform and otherwise requires copy/paste in all (and hence a possible point of failure) e.g. MCIP init is called from 2 platforms currently (axs10x and sim) which will go away once we have this. This change only adds the hooks but they are empty for now. Next commit will populate them and remove the explicit init calls from platforms. Signed-off-by: Vineet Gupta

ARC: boot log: move helper macros to header for reuse

2015-10-17T12:18:25Z

Signed-off-by: Vineet Gupta

ARCv2: spinlock/rwlock/atomics: Delayed retry of failed SCOND with exponential backoff

2015-08-04T03:56:34Z

This is to workaround the llock/scond livelock HS38x4 could get into a LLOCK/SCOND livelock in case of multiple overlapping coherency transactions in the SCU. The exclusive line state keeps rotating among contenting cores leading to a never ending cycle. So break the cycle by deferring the retry of failed exclusive access (SCOND). The actual delay needed is function of number of contending cores as well as the unrelated coherency traffic from other cores. To keep the code simple, start off with small delay of 1 which would suffice most cases and in case of contention double the delay. Eventually the delay is sufficient such that the coherency pipeline is drained, thus a subsequent exclusive access would succeed. Link: http://lkml.kernel.org/r/1438612568-28265-1-git-send-email-vgupta@synopsys.com Acked-by: Peter Zijlstra (Intel) Signed-off-by: Vineet Gupta

ARCv2: Fix the peripheral address space detection

2015-08-03T14:04:07Z

With HS 2.1 release, the peripheral space register no longer contains the uncached space specifics, causing the kernel to panic early on. So read the newer NON VOLATILE AUX register to get that info. Signed-off-by: Vineet Gupta

ARCv2: support HS38 releases

2015-07-13T08:03:23Z

Signed-off-by: Vineet Gupta