linux/arch/arm/include/asm/memory.h, branch v4.5

ARM: 8430/1: use default ioremap alignment for SMP or LPAE

2015-09-22T07:13:57Z

16MB alignment for ioremap mappings was added by commit a069c896d0d6 ("[ARM] 3705/1: add supersection support to ioremap()") in order to support supersection mappings. But __arm_ioremap_pfn_caller uses section and supersection mappings only in !SMP && !LPAE case. There is no need for such big alignment if either SMP or LPAE is enabled. After this change, ioremap will use default maximum alignment of 128 pages. Link: https://lkml.kernel.org/g/1419328813-2211-1-git-send-email-d.safonov@partner.samsung.com Cc: Guan Xuetao Cc: Nicolas Pitre Cc: James Bottomley Cc: Will Deacon Cc: Arnd Bergmann Cc: Catalin Marinas Cc: Andrew Morton Cc: Dmitry Safonov Signed-off-by: Sergey Dyasly Signed-off-by: Russell King

mm: move __phys_to_pfn and __pfn_to_phys to asm/generic/memory_model.h

2015-08-27T23:40:58Z

Three architectures already define these, and we'll need them genericly soon. Signed-off-by: Christoph Hellwig Signed-off-by: Dan Williams

ARM: fix __virt_to_idmap build error on !MMU

2015-07-17T14:08:40Z

Fengguang Wu reports that building ARM with !MMU results in the following build error: arch/arm/kernel/built-in.o: In function `__soft_restart': >> :(.text+0x1624): undefined reference to `arch_virt_to_idmap' Fix this by adding an appropriate IS_ENABLED(CONFIG_MMU) into the __virt_to_idmap() inline function. Signed-off-by: Russell King

Merge branches 'fixes' and 'ioremap' into for-linus

2015-07-07T11:35:33Z

ARM: 8396/1: use phys_addr_t in pfn_to_kaddr()

2015-06-29T10:16:09Z

This patch fixes pfn_to_kaddr() to use phys_addr_t. Without this, this macro is broken on LPAE systems. For physical addresses above first 4GB result of shifting pfn with PAGE_SHIFT may be truncated. Signed-off-by: Vitaly Andrianov Acked-by: Nicolas Pitre Acked-by: Santosh Shilimkar Signed-off-by: Russell King

ARM: redo TTBR setup code for LPAE

2015-06-01T22:48:19Z

Re-engineer the LPAE TTBR setup code. Rather than passing some shifted address in order to fit in a CPU register, pass either a full physical address (in the case of r4, r5 for TTBR0) or a PFN (for TTBR1). This removes the ARCH_PGD_SHIFT hack, and the last dangerous user of cpu_set_ttbr() in the secondary CPU startup code path (which was there to re-set TTBR1 to the appropriate high physical address space on Keystone2.) Tested-by: Murali Karicheri Signed-off-by: Russell King

ARM: Use include/asm-generic/io.h

2014-11-10T14:59:23Z

Include the generic I/O header file so that duplicate implementations can be removed. This will also help to establish consistency across more architectures regarding which accessors they support. Signed-off-by: Thierry Reding

Merge branch 'devel-stable' into for-next

2014-08-05T09:27:25Z

Conflicts: arch/arm/kernel/perf_event_cpu.c

ARM: 8113/1: remove remaining definitions of PLAT_PHYS_OFFSET from

2014-07-29T22:08:52Z

The platforms selecting NEED_MACH_MEMORY_H defined the start address of their physical memory in the respective . With ARM_PATCH_PHYS_VIRT=y (which is quite common today) this is useless though because the definition isn't used but determined dynamically. So remove the definitions from all and provide the Kconfig symbol PHYS_OFFSET with the respective defaults in case ARM_PATCH_PHYS_VIRT isn't enabled. This allows to drop the dependency of PHYS_OFFSET on !NEED_MACH_MEMORY_H which prevents compiling an integrator nommu-kernel. (CONFIG_PAGE_OFFSET which has "default PHYS_OFFSET if !MMU" expanded to "0x" because CONFIG_PHYS_OFFSET doesn't exist as INTEGRATOR selects NEED_MACH_MEMORY_H.) Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King

ARM: nommu: don't limit TASK_SIZE

2014-07-01T09:12:08Z

With TASK_SIZE set to the maximal RAM address booting in some XIP configurations fails (e.g. on efm32 DK3750). The problem is that strncpy_from_user et al. check for the address not being above TASK_SIZE (since 8c56cc8be5b3 (ARM: 7449/1: use generic strnlen_user and strncpy_from_user functions)) and this makes booting fail if the XIP flash is above the RAM address space. This change is in line with blackfin, frv and m68k which also use 0xffffffff for TASK_SIZE with !MMU. Signed-off-by: Uwe Kleine-König