<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/arch/arm/include/debug, branch v4.9</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.9</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.9'/>
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<updated>2016-08-08T18:14:09Z</updated>
<entry>
<title>ARM: brcmstb: Add earlyprintk support using run-time checks</title>
<updated>2016-08-08T18:14:09Z</updated>
<author>
<name>Florian Fainelli</name>
<email>f.fainelli@gmail.com</email>
</author>
<published>2016-06-28T19:18:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d0cf9d8a3c78cf70e3a78e898fdc1b2adea0e6dd'/>
<id>urn:sha1:d0cf9d8a3c78cf70e3a78e898fdc1b2adea0e6dd</id>
<content type='text'>
The SUN_TOP_CTRL_FAMILY_ID register  is at a fixed absolute address for
all of our supported chips, so utilize its value to determine what the
UARTA base address should be based on the value we read.

Since the code is called both during decompressor when the MMU is off,
and after the MMU has been turned on in the kernel, and we want to do
the lookup only once, we use the same technique as tegra.S and have a
shared storage location between the decompressor and the kernel.

Signed-off-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
</content>
</entry>
<entry>
<title>ARM: clps711x: Reduce static map size</title>
<updated>2016-07-06T15:38:52Z</updated>
<author>
<name>Alexander Shiyan</name>
<email>shc_work@mail.ru</email>
</author>
<published>2016-06-04T07:09:53Z</published>
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<id>urn:sha1:32981ea5b98682a70fdd27f2246fcd2c4e10126b</id>
<content type='text'>
Last CLPS711X CPU register is PLLR has 0xa5a8 address, so we can reduce
the map to 48k and align the end of the static at VMALLOC_START.

Signed-off-by: Alexander Shiyan &lt;shc_work@mail.ru&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'samsung-soc-4.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/soc</title>
<updated>2016-07-06T05:41:01Z</updated>
<author>
<name>Olof Johansson</name>
<email>olof@lixom.net</email>
</author>
<published>2016-07-06T05:41:01Z</published>
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<id>urn:sha1:553228d073444ac49cb24cafdde3e8a3fc56297a</id>
<content type='text'>
Samsung mach/soc update for v4.8, part 2:
1. Endian-friendly fixes.
2. Maintainers update.

* tag 'samsung-soc-4.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  MAINTAINERS: Extend Samsung SoC entry with S3C/S5P drivers
  ARM: SAMSUNG: Fix missing s5p_init_cpu() declaration
  ARM: EXYNOS: Fix UART address selection for DEBUG_LL
  ARM: EXYNOS: Fixup for __raw operations in suspend.c
  ARM: SAMSUNG: Fixup usage of __raw IO in PM
  ARM: EXYNOS: Fixup endian in pm/pmu
  ARM: EXYNOS: Fixups for big-endian operation
  ARM: SAMSUNG: Fixup endian issues in CPU detection
  ARM: EXYNOS: Fixup debug macros for big-endian
  ARM: s3c24xx: Sort cpufreq tables
  ARM: SAMSUNG: Fix typos

Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
</entry>
<entry>
<title>ARM: EXYNOS: Fix UART address selection for DEBUG_LL</title>
<updated>2016-06-22T06:20:43Z</updated>
<author>
<name>Joonyoung Shim</name>
<email>jy0922.shim@samsung.com</email>
</author>
<published>2014-09-26T10:43:54Z</published>
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<id>urn:sha1:2f3428b5cf9ba4255d8729fd249cbfb8a540d33e</id>
<content type='text'>
The Exynos542x SoCs using A15+A7 can boot to A15 or A7. If it boots using
A7 (like on Odroid XU family boards), it can't choose right UART
physical address only the part number of CP15. Fix the detection logic
by checking the Cluster ID additionally.

Signed-off-by: Joonyoung Shim &lt;jy0922.shim@samsung.com&gt;
Tested-by: Marek Szyprowski &lt;m.szyprowski@samsung.com&gt;
[k.kozlowski: Extend commit message]
Signed-off-by: Krzysztof Kozlowski &lt;k.kozlowski@samsung.com&gt;
</content>
</entry>
<entry>
<title>ARM: EXYNOS: Fixup debug macros for big-endian</title>
<updated>2016-06-21T11:08:09Z</updated>
<author>
<name>Ben Dooks</name>
<email>ben.dooks@codethink.co.uk</email>
</author>
<published>2016-06-21T10:20:22Z</published>
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<id>urn:sha1:4fdfa8623d0a3aca30da57980b14d1686c48c2d5</id>
<content type='text'>
The exynos low-level debug macros need to be fixed if the system is being
built big endian. Add the necessary endian swaps for accessing the registers
to get output working again

Signed-off-by: Ben Dooks &lt;ben.dooks@codethink.co.uk&gt;
Signed-off-by: Krzysztof Kozlowski &lt;k.kozlowski@samsung.com&gt;
</content>
</entry>
<entry>
<title>ARM: at91: debug: use DEBUG_UART_VIRT</title>
<updated>2016-06-10T15:08:56Z</updated>
<author>
<name>Alexandre Belloni</name>
<email>alexandre.belloni@free-electrons.com</email>
</author>
<published>2016-06-07T15:24:39Z</published>
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<id>urn:sha1:0b37e9e8dc02ab68bfb6ba0b5153be681886abd2</id>
<content type='text'>
AT91 still uses an offset (0x0100 0000) from the physical address to map
the debug UART. This is unfortunate as for some platforms (sama5d3 and
earlier), it ends up in the PCI zone and PCI is enabled in multi_v7.
Switch to DEBUG_UART_VIRT to solve that.

Tested on sama5d3 and 9g20.

Acked-by: Nicolas Ferre &lt;nicolas.ferre@atmel.com&gt;
Signed-off-by: Alexandre Belloni &lt;alexandre.belloni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'imx-soc-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc</title>
<updated>2016-03-02T22:30:17Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2016-03-02T22:30:17Z</published>
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<id>urn:sha1:f3a186fbfd413f2453c511da2dbcdc594c87dbde</id>
<content type='text'>
Merge "i.MX SoC update for 4.6" from Shawn Guo:

- Enable big endian mode support for i.MX platform
- Add support for i.MX6QP SoC which is the latest i.MX6 family addition
- Add basic suspend/resume support for i.MX25
- A couple of i.MX7D support updates
- A few random code cleanups

* tag 'imx-soc-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx: Make reset_control_ops const
  ARM: imx: Do L2 errata only if the L2 cache isn't enabled
  ARM: imx: select ARM_CPU_SUSPEND only for imx6
  ARM: mx25: Add basic suspend/resume support
  ARM: imx: Add msl code support for imx6qp
  ARM: imx: enable big endian mode
  ARM: imx: use endian-safe readl/readw/writel/writew
  ARM: imx7d: correct chip version information
  ARM: imx: select HAVE_ARM_ARCH_TIMER if selected i.MX7D
  ARM: imx6: fix cleanup path in imx6q_suspend_init()
</content>
</entry>
<entry>
<title>ARM: at91: avoid defining CONFIG_* symbols in source code</title>
<updated>2016-03-02T16:31:08Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2016-02-23T14:39:38Z</published>
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<id>urn:sha1:e91fb3bd757569aca48785358a4adbf41334d382</id>
<content type='text'>
In an invalid randconfig build (fixed by another patch),
I ran across this warning:

arch/arm/include/debug/at91.S:18:0: error: "CONFIG_DEBUG_UART_VIRT" redefined [-Werror]
 #define CONFIG_DEBUG_UART_VIRT AT91_IO_P2V(CONFIG_DEBUG_UART_PHYS)

As Russell pointed out, we should never #define a macro starting
with CONFIG_ in a source file, as that is rather confusing.

This renames the macro to avoid the symbol clash.

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Suggested-by: Russell King &lt;linux@arm.linux.org.uk&gt;
Acked-by: Alexandre Belloni &lt;alexandre.belloni@free-electrons.com&gt;
Acked-by: Nicolas Ferre &lt;nicolas.ferre@atmel.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'zynq-soc-for-4.6' of https://github.com/Xilinx/linux-xlnx into next/soc</title>
<updated>2016-02-26T21:54:53Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2016-02-26T21:54:53Z</published>
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<id>urn:sha1:e7ada8dfd564d9fa518432a513994cc53e358fad</id>
<content type='text'>
Merge "ARM: Xilinx Zynq patches for v4.6" from Michal Simek:

- SLCR early init
- Fix L2 cache data corruption
- Fix early printk uart setting

* tag 'zynq-soc-for-4.6' of https://github.com/Xilinx/linux-xlnx:
  ARM: zynq: Move early printk virtual address to vmalloc area
  ARM: zynq: address L2 cache data corruption
  ARM: zynq: initialize slcr mapping earlier
</content>
</entry>
<entry>
<title>ARM: zynq: Move early printk virtual address to vmalloc area</title>
<updated>2016-02-25T13:06:03Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2016-02-15T09:17:47Z</published>
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<id>urn:sha1:8fff2f752f2c9d31414f83170157701b59aec4c1</id>
<content type='text'>
The patch
"ARM: 8432/1: move VMALLOC_END from 0xff000000 to 0xff800000"
(sha1: 6ff0966052c46efb53980b8a1add2e7b49c9f560)
has moved also start of VMALLOC area because size didn't change.
That's why origin location of vmalloc was
   vmalloc : 0xf0000000 - 0xff000000   ( 240 MB)
and now is
   vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)

That's why uart virtual addresses need to be changed to reflect this new
memory setup. Starting address should be vmalloc start address.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
</feed>
