<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/arch/arm64/include/asm/sysreg.h, branch v4.2</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.2</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.2'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2014-07-25T12:12:15Z</updated>
<entry>
<title>arm64: gicv3: Allow GICv3 compilation with older binutils</title>
<updated>2014-07-25T12:12:15Z</updated>
<author>
<name>Catalin Marinas</name>
<email>catalin.marinas@arm.com</email>
</author>
<published>2014-07-24T13:14:42Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=72c5839515260dce966cd24f54436e6583288e6c'/>
<id>urn:sha1:72c5839515260dce966cd24f54436e6583288e6c</id>
<content type='text'>
GICv3 introduces new system registers accessible with the full msr/mrs
syntax (e.g. mrs x0, Sop0_op1_CRm_CRn_op2). However, only recent
binutils understand the new syntax. This patch introduces msr_s/mrs_s
assembly macros which generate the equivalent instructions above and
converts the existing GICv3 code (both drivers/irqchip/ and
arch/arm64/kernel/).

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Reported-by: Olof Johansson &lt;olof@lixom.net&gt;
Tested-by: Olof Johansson &lt;olof@lixom.net&gt;
Suggested-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Acked-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Acked-by: Jason Cooper &lt;jason@lakedaemon.net&gt;
Cc: Will Deacon &lt;will.deacon@arm.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
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