linux/arch/microblaze/kernel/entry.S, branch v3.5

Merge branch 'next' of git://git.monstr.eu/linux-2.6-microblaze

2012-05-28T16:49:56Z

Pull microblaze changes from Michal Simek. * 'next' of git://git.monstr.eu/linux-2.6-microblaze: microblaze: Setup correct pointer to TLS area microblaze: Add TLS support to sys_clone microblaze: ftrace: Pass the first calling instruction for dynamic ftrace microblaze: Port OOM changes to do_page_fault microblaze: Do not select GENERIC_GPIO by default

microblaze: Add TLS support to sys_clone

2012-05-25T04:40:23Z

Formerly unused Args 4/5 now load parent tid / child tid so the brid to do_fork can pick up TLS from r10. Arg 3 still unused There is also necessary to fix old glibc which do not setup r9/r10 (arg 4/5). Simple clearing them is fine. Signed-off-by: Edgar E. Iglesias Signed-off-by: David Holsgrove Signed-off-by: Michal Simek

microblaze: drop 'oldset' argument of do_notify_resume()

2012-05-22T03:59:48Z

never used... Signed-off-by: Al Viro

microblaze: handle TIF_NOTIFY_RESUME

2012-05-22T03:59:47Z

Signed-off-by: Al Viro

microblaze: Trivial asm fix

2012-01-05T07:34:28Z

Just replace one dot with comma. New binutils can detect it. Signed-off-by: Michal Simek

microblaze: Do not copy reset vectors/manual reset vector setup

2011-03-15T09:59:00Z

Reset vector can be setup by bootloader and kernel doens't need to touch it. If you require to setup reset vector, please use CONFIG_MANUAL_RESET_VECTOR throught menuconfig. It is not possible to setup address 0x0 as reset address because make no sense to set it up at all. Signed-off-by: Michal Simek Signed-off-by: John Williams

microblaze: Fix _reset function

2011-03-15T09:58:44Z

If soft reset falls through with no hardware assisted reset, the best we can do is jump to the reset vector and see what the bootloader left for us. Signed-off-by: Michal Simek Signed-off-by: John Williams

microblaze: Fix microblaze init vectors

2011-03-15T09:58:34Z

Microblaze vector table stores several vectors (reset, user exception, interrupt, debug exception and hardware exception). All these functions can be below address 0x10000. If they are, wrong vector table is genarated because jump is not setup from two instructions (imm upper 16bit and brai lower 16bit). Adding specific offset prevent problem if address is below 0x10000. For this case only brai instruction is used. Signed-off-by: Michal Simek

microblaze: Do not use "la" pseudo instruction - use addik instead

2011-03-09T07:09:54Z

"la" pseudo instruction is only translation to "addik". Use directly "addik" which is described in the MB reference guide. Signed-off-by: Michal Simek

microblaze: Remove r0_ram pointer and PTO alignment

2011-03-09T07:09:54Z

r0_ram pool was used for saving/restoring register content if hw exception happen. This poll was replaced by pt_pool_space with PT_SIZE size. Based on this change SAVE_STATE_ARG_SPACE was removed which caused that PTO offset is zero that's why is also removed. r0_ram space was used as scratchpad by v850. In early Microblaze Linux developing phase was this part of code blindly copied. Signed-off-by: Michal Simek