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<title>linux/arch/microblaze/kernel/hw_exception_handler.S, branch v3.5</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v3.5</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v3.5'/>
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<updated>2012-03-23T08:28:19Z</updated>
<entry>
<title>microblaze: Handle TLB skip size dynamically</title>
<updated>2012-03-23T08:28:19Z</updated>
<author>
<name>Michal Simek</name>
<email>monstr@monstr.eu</email>
</author>
<published>2010-02-08T15:41:38Z</published>
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<id>urn:sha1:e02db0aa3e1976ae4e23a66077d252a2f3ba74c7</id>
<content type='text'>
This patch fix the problem with rootfs on JFFS2 with early printk
console turned on.

The origin version used TLB63 for temporary early printk mapping.
The code expect that kernel is not able to use all 64 TLB entries
till early printk console is remapped by ioremap. After that
temporary mapping on TLB63 is silently lost.
This expectation give the opportunity to have early console pretty
early.

Microblaze systems with JFFS2 rootfs with early printk console turned on
used more than 64 TLB entries before kernel can remap early console.
Based on that kernel does access to bad area because early printk mapping
is rewritten.

This patch introduces tlb_skip variable which dynamically stores number
of skipped TLB entries from the TLB0. skip_tlb=2 means that TLB0 and TLB1
should be skipped.

MICROBLAZE_TLB_SKIP defines how many TLB is skipped at the kernel start.
They can be used for user purpose.

TLB 63 is used for temporary LMB mapping (MICROBLAZE_LMB_TLB_ID).

Also clean TLBLO when kernel starts.

For specific kernel sizes kernel can use just one TLB. Detect this case
and use the second TLB for general purpose.

Change _tlbia function to flush TLB entries from tlb_skip to TLB_SIZE.

Export tlb_skip size through debugfs.

Signed-off-by: Michal Simek &lt;monstr@monstr.eu&gt;
</content>
</entry>
<entry>
<title>microblaze: Introduce TLB skip size</title>
<updated>2012-03-23T08:28:18Z</updated>
<author>
<name>Michal Simek</name>
<email>monstr@monstr.eu</email>
</author>
<published>2011-04-04T13:46:03Z</published>
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<id>urn:sha1:1451d1d88b9aa32ac9ee54180239e9b34b6f9e86</id>
<content type='text'>
TLB skip size direct how many TLBs is skipped.
Currently TLB0 and TLB1 are used for Linux kernel mapping
that's why their are skipped.

Signed-off-by: Michal Simek &lt;monstr@monstr.eu&gt;
</content>
</entry>
<entry>
<title>microblaze: Fix unaligned value saving to the stack for system with MMU</title>
<updated>2011-07-25T07:07:45Z</updated>
<author>
<name>Michal Simek</name>
<email>monstr@monstr.eu</email>
</author>
<published>2011-05-20T07:02:13Z</published>
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<id>urn:sha1:c11389406f19e4bddc7b347e5259aebda02b23f1</id>
<content type='text'>
Several registers weren't saved correctly to the stack.

Unaligned expection for system with MMU stores
value in ex_tmp_data_loc_X address which is load to registers r3.
The next step is to move this value from r3 to a destination
register which caused unaligned exception. For several registers
this value was directly moved to the register.

For example for r28:
by "or r28, r0, r3"

but register r28 was rewritten when kernel returns from exception
handler by value saved on stack.

This patch changed r3 saving to the correct address on the stack.
For example for r28:
by "swi r3, r1, 4 * 28"

When kernel returns from the exception handler, correct value is restored.

Signed-off-by: Michal Simek &lt;monstr@monstr.eu&gt;
</content>
</entry>
<entry>
<title>microblaze: Do not use "la" pseudo instruction - use addik instead</title>
<updated>2011-03-09T07:09:54Z</updated>
<author>
<name>Michal Simek</name>
<email>monstr@monstr.eu</email>
</author>
<published>2011-02-01T08:00:57Z</published>
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<id>urn:sha1:cd3415779bdb13e3daaf13965c89d286a0cf0480</id>
<content type='text'>
"la" pseudo instruction is only translation to "addik".
Use directly "addik" which is described in the MB reference guide.

Signed-off-by: Michal Simek &lt;monstr@monstr.eu&gt;
</content>
</entry>
<entry>
<title>microblaze: Remove r0_ram pointer and PTO alignment</title>
<updated>2011-03-09T07:09:54Z</updated>
<author>
<name>Michal Simek</name>
<email>monstr@monstr.eu</email>
</author>
<published>2011-01-31T14:10:04Z</published>
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<id>urn:sha1:6e83557c38b40d6e9d1c82ad0ae59d8e5db9c50c</id>
<content type='text'>
r0_ram pool was used for saving/restoring register
content if hw exception happen. This poll was replaced by
pt_pool_space with PT_SIZE size.
Based on this change SAVE_STATE_ARG_SPACE was removed which
caused that PTO offset is zero that's why is also removed.

r0_ram space was used as scratchpad by v850. In early
Microblaze Linux developing phase was this part of code
blindly copied.

Signed-off-by: Michal Simek &lt;monstr@monstr.eu&gt;
</content>
</entry>
<entry>
<title>microblaze: Do not use r0_ram space for hw exception debugging</title>
<updated>2011-03-09T07:09:53Z</updated>
<author>
<name>Michal Simek</name>
<email>monstr@monstr.eu</email>
</author>
<published>2011-01-31T14:07:53Z</published>
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<id>urn:sha1:c06b3a068223cb885d85ac4f6c31e870ca2b5aac</id>
<content type='text'>
Remove hw exception counting space from r0_ram. Use special
exception_debug_table poll for exception statistic.

Signed-off-by: Michal Simek &lt;monstr@monstr.eu&gt;
</content>
</entry>
<entry>
<title>microblaze: Fix unaligned issue on MMU system with BS=0 DIV=1</title>
<updated>2011-01-28T13:05:00Z</updated>
<author>
<name>Michal Simek</name>
<email>monstr@monstr.eu</email>
</author>
<published>2011-01-28T12:14:58Z</published>
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<id>urn:sha1:9c749e177ccc0b3ee9589425c7255079e7a726fc</id>
<content type='text'>
Unaligned code use shift for finding register operand.
There is used BSRLI(r8,r8,2) macro which is expand for BS=0, DIV=1
by
	ori rD, r0, (1 &lt;&lt; imm);	\
	idivu rD, rD, rA

but if rD is equal rA then ori instruction rewrite value which
should be devide.

The patch remove this macro which use idivu instruction because
idivu takes 32/34 cycles. The highest shifting is 20 which takes
20 cycles.

Signed-off-by: Michal Simek &lt;monstr@monstr.eu&gt;
</content>
</entry>
<entry>
<title>microblaze: Fix unaligned exception for little endian platform</title>
<updated>2011-01-03T09:08:29Z</updated>
<author>
<name>Michal Simek</name>
<email>monstr@monstr.eu</email>
</author>
<published>2010-12-29T13:34:46Z</published>
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<id>urn:sha1:e3288f310111f7d18c323d95ae998765dee8c825</id>
<content type='text'>
Half word unaligned accesses need to be fixed.

Signed-off-by: Michal Simek &lt;monstr@monstr.eu&gt;
</content>
</entry>
<entry>
<title>microblaze: Add stack unwinder</title>
<updated>2010-08-04T08:22:35Z</updated>
<author>
<name>Steven J. Magnani</name>
<email>steve@digidescorp.com</email>
</author>
<published>2010-04-27T17:37:54Z</published>
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<id>urn:sha1:ce3266c047389443d5f433d605c769e878cbe46e</id>
<content type='text'>
Implement intelligent backtracing by searching for stack frame creation,
and emitting only return addresses. Use print_hex_dump() to display the
entire binary kernel stack.

Limitation: MMU kernels are not currently able to trace beyond a system trap
(interrupt, syscall, etc.). It is the intent of this patch to provide
infrastructure that can be extended to add this capability later.

Changes from V1:
* Removed checks in find_frame_creation() that prevented location of the frame
  creation instruction in heavily optimized code
* Various formatting/commenting/file location tweaks per review comments
* Dropped Kconfig option to enable STACKTRACE as something logically separate

Signed-off-by: Steven J. Magnani &lt;steve@digidescorp.com&gt;
</content>
</entry>
<entry>
<title>microblaze: Use instruction with delay slot</title>
<updated>2010-04-01T06:38:23Z</updated>
<author>
<name>Michal Simek</name>
<email>monstr@monstr.eu</email>
</author>
<published>2010-03-22T19:43:27Z</published>
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<id>urn:sha1:3765d6958dfff34a15588e23c5d1274e1f6ba200</id>
<content type='text'>
Sync labels.

Signed-off-by: Michal Simek &lt;monstr@monstr.eu&gt;
</content>
</entry>
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