linux/arch/microblaze/kernel/hw_exception_handler.S, branch v3.8

microblaze: Remove additional andi which has been already done

2012-10-04T12:52:54Z

Remove one additional step. Signed-off-by: Michal Simek

microblaze: Use predefined macro for ESR_DIZ

2012-10-04T12:52:53Z

Just use macro instead of hardcoded value. Signed-off-by: Michal Simek

microblaze: Support 4k/16k/64k pages

2012-10-04T12:52:49Z

Add support for page size which is supported by MMU. Remove 8k and 32k page size because they are not supported by MMU. Signed-off-by: Michal Simek

microblaze: Do not used hardcoded value in exception handler

2012-10-04T12:47:01Z

Use predefined macros to support more page sizes. Signed-off-by: Michal Simek

microblaze: Handle TLB skip size dynamically

2012-03-23T08:28:19Z

This patch fix the problem with rootfs on JFFS2 with early printk console turned on. The origin version used TLB63 for temporary early printk mapping. The code expect that kernel is not able to use all 64 TLB entries till early printk console is remapped by ioremap. After that temporary mapping on TLB63 is silently lost. This expectation give the opportunity to have early console pretty early. Microblaze systems with JFFS2 rootfs with early printk console turned on used more than 64 TLB entries before kernel can remap early console. Based on that kernel does access to bad area because early printk mapping is rewritten. This patch introduces tlb_skip variable which dynamically stores number of skipped TLB entries from the TLB0. skip_tlb=2 means that TLB0 and TLB1 should be skipped. MICROBLAZE_TLB_SKIP defines how many TLB is skipped at the kernel start. They can be used for user purpose. TLB 63 is used for temporary LMB mapping (MICROBLAZE_LMB_TLB_ID). Also clean TLBLO when kernel starts. For specific kernel sizes kernel can use just one TLB. Detect this case and use the second TLB for general purpose. Change _tlbia function to flush TLB entries from tlb_skip to TLB_SIZE. Export tlb_skip size through debugfs. Signed-off-by: Michal Simek

microblaze: Introduce TLB skip size

2012-03-23T08:28:18Z

TLB skip size direct how many TLBs is skipped. Currently TLB0 and TLB1 are used for Linux kernel mapping that's why their are skipped. Signed-off-by: Michal Simek

microblaze: Fix unaligned value saving to the stack for system with MMU

2011-07-25T07:07:45Z

Several registers weren't saved correctly to the stack. Unaligned expection for system with MMU stores value in ex_tmp_data_loc_X address which is load to registers r3. The next step is to move this value from r3 to a destination register which caused unaligned exception. For several registers this value was directly moved to the register. For example for r28: by "or r28, r0, r3" but register r28 was rewritten when kernel returns from exception handler by value saved on stack. This patch changed r3 saving to the correct address on the stack. For example for r28: by "swi r3, r1, 4 * 28" When kernel returns from the exception handler, correct value is restored. Signed-off-by: Michal Simek

microblaze: Do not use "la" pseudo instruction - use addik instead

2011-03-09T07:09:54Z

"la" pseudo instruction is only translation to "addik". Use directly "addik" which is described in the MB reference guide. Signed-off-by: Michal Simek

microblaze: Remove r0_ram pointer and PTO alignment

2011-03-09T07:09:54Z

r0_ram pool was used for saving/restoring register content if hw exception happen. This poll was replaced by pt_pool_space with PT_SIZE size. Based on this change SAVE_STATE_ARG_SPACE was removed which caused that PTO offset is zero that's why is also removed. r0_ram space was used as scratchpad by v850. In early Microblaze Linux developing phase was this part of code blindly copied. Signed-off-by: Michal Simek

microblaze: Do not use r0_ram space for hw exception debugging

2011-03-09T07:09:53Z

Remove hw exception counting space from r0_ram. Use special exception_debug_table poll for exception statistic. Signed-off-by: Michal Simek