<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/arch/mips/generic, branch v5.12</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.12</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.12'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2021-02-04T12:34:51Z</updated>
<entry>
<title>MIPS: of: Introduce helper function to get DTB</title>
<updated>2021-02-04T12:34:51Z</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2021-01-27T13:24:30Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b83ba0b9df56f8404ccc6ebcc7050fb8294f0f20'/>
<id>urn:sha1:b83ba0b9df56f8404ccc6ebcc7050fb8294f0f20</id>
<content type='text'>
Selection of the DTB to be used was burried in more or less readable
code in head.S. Move this code into a inline helper function and
use it.

Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
Acked-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
</content>
</entry>
<entry>
<title>MIPS: Remove empty prom_free_prom_memory functions</title>
<updated>2021-01-07T16:11:33Z</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2021-01-05T21:36:31Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a6e83acee2dd377959ec4bdeaa463da45ba0f811'/>
<id>urn:sha1:a6e83acee2dd377959ec4bdeaa463da45ba0f811</id>
<content type='text'>
Most of the prom_free_prom_memory functions are empty. With
a new weak prom_free_prom_memory() we can remove all of them.

Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
Acked-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: Add serval support</title>
<updated>2020-11-12T22:35:15Z</updated>
<author>
<name>Gregory CLEMENT</name>
<email>gregory.clement@bootlin.com</email>
</author>
<published>2020-11-10T11:45:08Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=fe0052018a84d50be034449b4175177f569fbf5c'/>
<id>urn:sha1:fe0052018a84d50be034449b4175177f569fbf5c</id>
<content type='text'>
Add a device trees and FIT image support for the Microsemi Serval SoC
which belongs to same family of the Ocelot SoC.

It is based on the work of Lars Povlsen &lt;lars.povlsen@microchip.com&gt;.

Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Acked-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: Add jaguar2 support</title>
<updated>2020-11-12T22:34:25Z</updated>
<author>
<name>Gregory CLEMENT</name>
<email>gregory.clement@bootlin.com</email>
</author>
<published>2020-11-10T11:45:07Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f84778f7d8c3b867d6aaca9361d7b43b222f9f6a'/>
<id>urn:sha1:f84778f7d8c3b867d6aaca9361d7b43b222f9f6a</id>
<content type='text'>
Add a device trees and FIT image support for the Microsemi Jaguar2 SoC
which belongs to same family of the Ocelot SoC.

It is based on the work of Lars Povlsen &lt;lars.povlsen@microchip.com&gt;.

Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Acked-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: build FIT image for Luton</title>
<updated>2020-11-12T22:34:03Z</updated>
<author>
<name>Gregory CLEMENT</name>
<email>gregory.clement@bootlin.com</email>
</author>
<published>2020-11-10T11:45:06Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=378e413fe97e8d66ff4dc90b0b5b6ef3bbc15252'/>
<id>urn:sha1:378e413fe97e8d66ff4dc90b0b5b6ef3bbc15252</id>
<content type='text'>
Luton now has already an u-boot port so let's build FIT images.

Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Acked-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: Fix configuration name for ocelot legacy boards</title>
<updated>2020-11-12T22:32:05Z</updated>
<author>
<name>Gregory CLEMENT</name>
<email>gregory.clement@bootlin.com</email>
</author>
<published>2020-11-10T11:45:03Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2825f4c0ffcdf6e519e30ecdae4cd8c1c89a1cb9'/>
<id>urn:sha1:2825f4c0ffcdf6e519e30ecdae4cd8c1c89a1cb9</id>
<content type='text'>
Ocelots is supported by the generic MIPS build so make it clears that
LEGACY_BOARD_OCELOT is only needed for legacy boards which didn't have
bootloader supporting device tree.

Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Acked-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: Prepare configuration to handle more SoCs</title>
<updated>2020-11-12T22:31:47Z</updated>
<author>
<name>Gregory CLEMENT</name>
<email>gregory.clement@bootlin.com</email>
</author>
<published>2020-11-10T11:45:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=700364dadceb8d60ca1bb6ccd3da619a36ecdcde'/>
<id>urn:sha1:700364dadceb8d60ca1bb6ccd3da619a36ecdcde</id>
<content type='text'>
Ocelot belongs to a family of SoC named the VCore III. In order to add
these new Soc, use the new symbol SOC_VCOREIII instead of a one
dedicated to Ocelot.

In order to avoid regression on driver building, the MSCC_OCELOT
configuration symbol is kept until the driver will be converted.

Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Acked-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Ingenic: Add system type for new Ingenic SoCs.</title>
<updated>2020-09-27T08:57:27Z</updated>
<author>
<name>周琰杰 (Zhou Yanjie)</name>
<email>zhouyanjie@wanyeetech.com</email>
</author>
<published>2020-09-22T01:24:43Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a9fee3a513e560b154ccbe662faa791d5f358875'/>
<id>urn:sha1:a9fee3a513e560b154ccbe662faa791d5f358875</id>
<content type='text'>
Add JZ4775, X1000E, X2000, and X2000E system type for cat /proc/cpuinfo
to give out JZ4775, X1000E, X2000 and X2000E.

Signed-off-by: 周琰杰 (Zhou Yanjie) &lt;zhouyanjie@wanyeetech.com&gt;
Reviewed-by: Paul Cercueil &lt;paul@crapouillou.net&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: jz4740: Rename jz4740 folders to ingenic</title>
<updated>2020-09-18T14:35:05Z</updated>
<author>
<name>Paul Cercueil</name>
<email>paul@crapouillou.net</email>
</author>
<published>2020-09-06T19:29:33Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a103e9b951f9094792fd0dab0a0dcd1b3408825a'/>
<id>urn:sha1:a103e9b951f9094792fd0dab0a0dcd1b3408825a</id>
<content type='text'>
Now that all the jz4740 platform code has been removed, and we're left
with only a Kconfig and the cpu-feature-overrides.h file, finalize the
cleanup process by renaming the jz4740 and include/mach-jz4740 folders
to ingenic and include/mach-ingenic.

Signed-off-by: Paul Cercueil &lt;paul@crapouillou.net&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: generic: Add support for Ingenic SoCs</title>
<updated>2020-09-18T14:33:59Z</updated>
<author>
<name>Paul Cercueil</name>
<email>paul@crapouillou.net</email>
</author>
<published>2020-09-06T19:29:31Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f0f4a753079c636d5d43a102edbde0dad1e7de51'/>
<id>urn:sha1:f0f4a753079c636d5d43a102edbde0dad1e7de51</id>
<content type='text'>
Add support for Ingenic SoCs in arch/mips/generic/.

The Kconfig changes are here to ensure that it is possible to compile
either a generic kernel that supports Ingenic SoCs, or a Ingenic-only
kernel, both using the same code base, to avoid duplicated code.

Signed-off-by: Paul Cercueil &lt;paul@crapouillou.net&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
</feed>
