<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/arch/mips/include/asm/cacheops.h, branch v4.5</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.5</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.5'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2016-01-24T02:29:58Z</updated>
<entry>
<title>MIPS: Break down cacheops.h definitions</title>
<updated>2016-01-24T02:29:58Z</updated>
<author>
<name>James Hogan</name>
<email>james.hogan@imgtec.com</email>
</author>
<published>2015-12-16T23:49:36Z</published>
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<id>urn:sha1:5fa393c8571953d6d428062c3572ec3ddbb1eec8</id>
<content type='text'>
Most of the cache op codes defined in cacheops.h are split into a 2-bit
cache identifier, and a 3-bit cache op code which does largely the same
thing semantically regardless of the cache identifier.

To allow the use of these definitions by KVM for decoding cache ops,
break the definitions down into parts where it makes sense to do so, and
add masks for the Cache and Op field within the cache op.

Signed-off-by: James Hogan &lt;james.hogan@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Cc: Gleb Natapov &lt;gleb@kernel.org&gt;
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11892/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: fix case mismatch in local_r4k_flush_icache_range()</title>
<updated>2014-01-15T07:19:42Z</updated>
<author>
<name>Huacai Chen</name>
<email>chenhc@lemote.com</email>
</author>
<published>2014-01-15T01:56:37Z</published>
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<id>urn:sha1:bad009fe354a00e6b2bf87328995ec76e59ab970</id>
<content type='text'>
Currently, Loongson-2 call protected_blast_icache_range() and others
call protected_loongson23_blast_icache_range(), but I think the correct
behavior should be the opposite.  BTW, Loongson-3's cache-ops is
compatible with MIPS64, but not compatible with Loongson-2.  So, rename
xxx_loongson23_yyy things to xxx_loongson2_yyy.

The patch fixes early boot hang with 3.13-rc1, introduced in commit
14bd8c082016 ("MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over
arch/mips").

Signed-off-by: Huacai Chen &lt;chenhc@lemote.com&gt;
Signed-off-by: Aaro Koskinen &lt;aaro.koskinen@iki.fi&gt;
Reviewed-by: Aurelien Jarno &lt;aurelien@aurel32.net&gt;
Acked-by: John Crispin &lt;blogic@openwrt.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips.</title>
<updated>2013-10-29T20:25:24Z</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2013-09-25T16:21:26Z</published>
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<id>urn:sha1:14bd8c082016cd1f67fdfd702e4cf6367869a712</id>
<content type='text'>
It was ugly.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: cacheops.h: Increase indentation by one tab.</title>
<updated>2013-10-29T20:25:22Z</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2013-09-27T17:07:18Z</published>
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<id>urn:sha1:7b784c634b4147345b46251884be6be4bd45fd43</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Whitespace cleanup.</title>
<updated>2013-02-01T09:00:22Z</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2013-01-22T11:59:30Z</published>
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<id>urn:sha1:7034228792cc561e79ff8600f02884bd4c80e287</id>
<content type='text'>
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: RM7000: Add support for tertiary cache</title>
<updated>2010-08-05T12:26:06Z</updated>
<author>
<name>Ricardo Mendoza</name>
<email>ricmm@gentoo.org</email>
</author>
<published>2010-07-19T04:00:00Z</published>
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<id>urn:sha1:745aef5df1e2277ee9e34d86491084c0d6106338</id>
<content type='text'>
Add support for the external T-cache interface. Allow for platform
independent size probing from 512KB to 8MB in powers of two.

Signed-off-by: Ricardo Mendoza &lt;ricmm@gentoo.org&gt;
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1477/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Move headfiles to new location below arch/mips/include</title>
<updated>2008-10-11T15:18:52Z</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2008-09-16T17:48:51Z</published>
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<id>urn:sha1:384740dc49ea651ba350704d13ff6be9976e37fe</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
</feed>
