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<title>linux/arch/mips/kernel/Makefile, branch v4.9</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.9</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.9'/>
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<updated>2016-08-02T09:02:35Z</updated>
<entry>
<title>MIPS: Factor o32 specific code into signal_o32.c</title>
<updated>2016-08-02T09:02:35Z</updated>
<author>
<name>Harvey Hunt</name>
<email>harvey.hunt@imgtec.com</email>
</author>
<published>2016-06-17T15:03:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d1e63c947a6fa4f61253343d9bbd834394a6c364'/>
<id>urn:sha1:d1e63c947a6fa4f61253343d9bbd834394a6c364</id>
<content type='text'>
The commit ebb5e78cc634 ("MIPS: Initial implementation of a VDSO")
caused building a 64 bit kernel with support for n32 and not o32
to produce a build error:

arch/mips/kernel/signal32.c:415:11: error: ‘vdso_image_o32’ undeclared here (not in a function)
  .vdso  = &amp;vdso_image_o32,

Fix this by moving the o32 specific code into signal_o32.c and
updating the Makefile accordingly.

Signed-off-by: Harvey Hunt &lt;harvey.hunt@imgtec.com&gt;
Cc: Leonid Yegoshin &lt;Leonid.Yegoshin@imgtec.com&gt;
Cc: Alex Smith &lt;alex@alex-smith.me.uk&gt;
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13690/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Kernel: Add relocate.c</title>
<updated>2016-05-13T12:02:02Z</updated>
<author>
<name>Matt Redfearn</name>
<email>matt.redfearn@imgtec.com</email>
</author>
<published>2016-03-31T09:05:36Z</published>
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<id>urn:sha1:279b991b24d2439fbe9d2f093988b9c8aed2603d</id>
<content type='text'>
arch/mips/kernel/relocate.c contains the functions necessary to relocate
the kernel elsewhere in memory

The kernel makes a copy of itself at the new address. It uses the
relocation table inserted by the relocs tool to fix symbol references
within the new image.

If copy/relocation is sucessful then the entry point of the new kernel
is returned, otherwise fall back to starting the kernel in place.

Signed-off-by: Matt Redfearn &lt;matt.redfearn@imgtec.com&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: James Hogan &lt;james.hogan@imgtec.com&gt;
Cc: Paul Burton &lt;paul.burton@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Cc: kernel-hardening@lists.openwall.com
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12985/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: BMIPS: Add Whirlwind (BMIPS5200) initialization code</title>
<updated>2016-05-09T10:00:01Z</updated>
<author>
<name>Florian Fainelli</name>
<email>f.fainelli@gmail.com</email>
</author>
<published>2016-02-04T02:14:50Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=21b30c00f3067001519eda166675c1958b163c91'/>
<id>urn:sha1:21b30c00f3067001519eda166675c1958b163c91</id>
<content type='text'>
Import bmips_5xxx_init.S from the stblinux-3.3 tree, and to make sure that this
would work nicely with a BMIPS multiplatform kernel (with BMIPS330, BMIPS43XX
and BMIPS5000 enabled), update soft_reset to check for the BMIPS5200 processor
id (PRID_IMP_BMIPS5200) and execute bmips_5xxx_init for these processors to
bring them online.

Tested on 7425, 7429 and 7435 with CPU hotplug. 7435 SMP still needs some
additional changes in the L1 interrupt area to work properly with interrupt
affinity.

Signed-off-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Cc: linux-mips@linux-mips.org
Cc: john@phrozen.org
Cc: cernekee@gmail.com
Cc: jon.fraser@broadcom.com
Cc: jaedon.shin@gmail.com
Cc: dragan.stancevic@gmail.com
Cc: jogo@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/12377/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Delete smp-gic.c</title>
<updated>2016-02-25T09:56:58Z</updated>
<author>
<name>Qais Yousef</name>
<email>qais.yousef@imgtec.com</email>
</author>
<published>2015-12-08T13:20:29Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7eb8c99db26cc6499bfb1eba72dffc4730570752'/>
<id>urn:sha1:7eb8c99db26cc6499bfb1eba72dffc4730570752</id>
<content type='text'>
We now have a generic IPI layer that will use GIC automatically
if it's compiled in.

Signed-off-by: Qais Yousef &lt;qais.yousef@imgtec.com&gt;
Acked-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: &lt;jason@lakedaemon.net&gt;
Cc: &lt;marc.zyngier@arm.com&gt;
Cc: &lt;jiang.liu@linux.intel.com&gt;
Cc: &lt;linux-mips@linux-mips.org&gt;
Cc: &lt;lisa.parratt@imgtec.com&gt;
Cc: Qais Yousef &lt;qsyousef@gmail.com&gt;
Link: http://lkml.kernel.org/r/1449580830-23652-19-git-send-email-qais.yousef@imgtec.com
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
</entry>
<entry>
<title>MIPS: CPS: Early debug using an ns16550-compatible UART</title>
<updated>2015-11-11T07:34:25Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2015-09-22T18:12:11Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=609cf6f2291a69d09aa5c02d74cd4488b19aa9a6'/>
<id>urn:sha1:609cf6f2291a69d09aa5c02d74cd4488b19aa9a6</id>
<content type='text'>
Provide support for outputting early debug information, in the form of
various register values should an exception occur, during the early
bringup of secondary cores. This code requires an ns16550-compatible
UART accessible from the secondary core, and is written in assembly due
to the environment in which such early exceptions occur where way may
not have a stack, be coherent or even have initialised caches.

[ralf@linux-mips.org: Fix merge conflict.]

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Cc: Steven J. Hill &lt;Steven.Hill@imgtec.com&gt;
Cc: Andrew Bresticker &lt;abrestic@chromium.org&gt;
Cc: Leonid Yegoshin &lt;Leonid.Yegoshin@imgtec.com&gt;
Cc: Maciej W. Rozycki &lt;macro@linux-mips.org&gt;
Cc: Jason Cooper &lt;jason@lakedaemon.net&gt;
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan &lt;james.hogan@imgtec.com&gt;
Cc: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/11202/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus</title>
<updated>2015-09-03T23:55:55Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2015-09-03T23:55:55Z</published>
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<id>urn:sha1:807249d3ada1ff28a47c4054ca4edd479421b671</id>
<content type='text'>
Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for 4.3 for MIPS.  Here's the summary:

  Three fixes that didn't make 4.2-stable:

   - a -Os build might compile the kernel using the MIPS16 instruction
     set but the R2 optimized inline functions in &lt;uapi/asm/swab.h&gt; are
     implemented using 32-bit wide instructions which is invalid.

   - a build error in pgtable-bits.h for a particular kernel
     configuration.

   - accessing registers of the CM GCR might have been compiled to use
     64 bit accesses but these registers are onl 32 bit wide.

  And also a few new bits:

   - move the ATH79 GPIO driver to drivers/gpio

   - the definition of IRQCHIP_DECLARE has moved to linux/irqchip.h,
     change ATH79 accordingly.

   - fix definition of pgprot_writecombine

   - add an implementation of dma_map_ops.mmap

   - fix alignment of quiet build output for vmlinuz link

   - BCM47xx: Use kmemdup rather than duplicating its implementation

   - Netlogic: Fix 0x0x prefixes of constants.

   - merge Bjorn Helgaas' series to remove most of the weak keywords
     from function declarations.

   - CP0 and CP1 registers are best considered treated as unsigned
     values to avoid large values from becoming negative values.

   - improve support for the MIPS GIC timer.

   - enable common clock framework for Malta and SEAD3.

   - a number of improvments and fixes to dump_tlb().

   - document the MIPS TLB dump functionality in Magic SysRq.

   - Cavium Octeon CN68XX improvments.

   - NetLogic improvments.

   - irq: Use access helper irq_data_get_affinity_mask.

   - handle MSA unaligned accesses.

   - a number of R6-related math-emu fixes.

   - support for I6400.

   - improvments to MSA support.

   - add uprobes support.

   - move from deprecated __initcall to arch_initcall.

   - remove finish_arch_switch().

   - IRQ cleanups by Thomas Gleixner.

   - migrate to new 'set-state' interface.

   - random small cleanups"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (148 commits)
  MIPS: UAPI: Fix unrecognized opcode WSBH/DSBH/DSHD when using MIPS16.
  MIPS: Fix alignment of quiet build output for vmlinuz link
  MIPS: math-emu: Remove unused handle_dsemul function declaration
  MIPS: math-emu: Add support for the MIPS R6 MAX{, A} FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 MIN{, A} FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 CLASS FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 RINT FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 SELNEZ FPU instruction
  MIPS: math-emu: Add support for the MIPS R6 SELEQZ FPU instruction
  MIPS: math-emu: Add support for the CMP.condn.fmt R6 instruction
  MIPS: inst.h: Add new MIPS R6 FPU opcodes
  MIPS: Octeon: Fix management port MII address on Kontron S1901
  MIPS: BCM47xx: Use kmemdup rather than duplicating its implementation
  STAGING: Octeon: Use common helpers for determining interface and port
  MIPS: Octeon: Support interfaces 4 and 5
  MIPS: Octeon: Set up 1:1 mapping between CN68XX PKO queues and ports
  MIPS: Octeon: Initialize CN68XX PKO
  STAGING: Octeon: Support CN68XX style WQE
  ...
</content>
</entry>
<entry>
<title>MIPS: Add uprobes support.</title>
<updated>2015-09-03T10:08:05Z</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2015-07-29T20:44:53Z</published>
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<id>urn:sha1:40e084a506eba78310cd5e8ab700fd1226c6130a</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS/irqchip: Move i8259 irqchip driver to drivers/irqchip</title>
<updated>2015-07-31T20:04:49Z</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2015-07-08T12:46:08Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0509cfde038d8afb0c1df1d52c90ae847b425d97'/>
<id>urn:sha1:0509cfde038d8afb0c1df1d52c90ae847b425d97</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
</entry>
<entry>
<title>MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip.</title>
<updated>2015-06-21T19:52:50Z</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2015-05-26T16:20:06Z</published>
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<id>urn:sha1:67e38cf2933e904426b428431961e4880d6d4b90</id>
<content type='text'>
While at it, rename it because in drivers/irqchip no longer every CPU is
a MIPS.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Add SysRq operation to dump TLBs on all CPUs</title>
<updated>2015-06-21T19:52:27Z</updated>
<author>
<name>James Hogan</name>
<email>james.hogan@imgtec.com</email>
</author>
<published>2015-05-19T08:50:29Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d1e9a4f547354ca258b6200ab6b1f0e4909b92e8'/>
<id>urn:sha1:d1e9a4f547354ca258b6200ab6b1f0e4909b92e8</id>
<content type='text'>
Add a MIPS specific SysRq operation to dump the TLB entries on all CPUs,
using the 'x' trigger key.

Signed-off-by: James Hogan &lt;james.hogan@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10072/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
</feed>
