linux/arch/riscv/include/asm/kvm_vcpu_insn.h, branch master

RISC-V: KVM: Add extensible CSR emulation framework

2022-07-29T11:44:53Z

We add an extensible CSR emulation framework which is based upon the existing system instruction emulation. This will be useful to upcoming AIA, PMU, Nested and other virtualization features. The CSR emulation framework also has provision to emulate CSR in user space but this will be used only in very specific cases such as AIA IMSIC CSR emulation in user space or vendor specific CSR emulation in user space. By default, all CSRs not handled by KVM RISC-V will be redirected back to Guest VCPU as illegal instruction trap. Signed-off-by: Anup Patel Signed-off-by: Anup Patel

RISC-V: KVM: Add extensible system instruction emulation framework

2022-07-29T11:44:46Z

We will be emulating more system instructions in near future with upcoming AIA, PMU, Nested and other virtualization features. To accommodate above, we add an extensible system instruction emulation framework in vcpu_insn.c. Signed-off-by: Anup Patel Signed-off-by: Anup Patel

RISC-V: KVM: Factor-out instruction emulation into separate sources

2022-07-29T11:44:40Z

The instruction and CSR emulation for VCPU is going to grow over time due to upcoming AIA, PMU, Nested and other virtualization features. Let us factor-out VCPU instruction emulation from vcpu_exit.c to a separate source dedicated for this purpose. Signed-off-by: Anup Patel Signed-off-by: Anup Patel