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<title>linux/arch/riscv/kernel/suspend_entry.S, branch master</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
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<updated>2026-04-05T00:42:44Z</updated>
<entry>
<title>riscv: Remove support for XIP kernel</title>
<updated>2026-04-05T00:42:44Z</updated>
<author>
<name>Nam Cao</name>
<email>namcao@linutronix.de</email>
</author>
<published>2026-04-04T01:28:48Z</published>
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<id>urn:sha1:9b3a2be84803cf18c4b4d1efc695991f0daa153c</id>
<content type='text'>
XIP has a history of being broken for long periods of time. In 2023, it was
broken for 18 months before getting fixed [1]. In 2024 it was 4 months [2].

And now it is broken again since commit a44fb5722199 ("riscv: Add runtime
constant support"), 10 months ago.

These are clear signs that XIP feature is not being used.

I occasionally looked after XIP, but mostly because I was bored and had
nothing better to do.

Remove XIP support. Revert is possible if someone shows up complaining.

Link: https://lore.kernel.org/linux-riscv/20231212-customary-hardcover-e19462bf8e75@wendy/ [1]
Link: https://lore.kernel.org/linux-riscv/20240526110104.470429-1-namcao@linutronix.de/ [2]
Signed-off-by: Nam Cao &lt;namcao@linutronix.de&gt;
Cc: Frederik Haxel &lt;haxel@fzi.de&gt;
Cc: Vitaly Wool &lt;vitaly.wool@konsulko.com&gt;
Reviewed-by: Jisheng Zhang &lt;jszhang@kernel.org&gt;
Acked-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://patch.msgid.link/20260202115403.2119218-1-namcao@linutronix.de
[pjw@kernel.org: updated to apply]
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;
</content>
</entry>
<entry>
<title>riscv: Use SYM_*() assembly macros instead of deprecated ones</title>
<updated>2023-11-06T17:42:47Z</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2023-10-24T13:26:52Z</published>
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<id>urn:sha1:76329c693924d8f37afbf361f0d8daab594e1644</id>
<content type='text'>
ENTRY()/END()/WEAK() macros are deprecated and we should make use of the
new SYM_*() macros [1] for better annotation of symbols. Replace the
deprecated ones with the new ones and fix wrong usage of END()/ENDPROC()
to correctly describe the symbols.

[1] https://docs.kernel.org/core-api/asm-annotations.html

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20231024132655.730417-3-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>riscv: Move global pointer loading to a macro</title>
<updated>2023-10-27T21:43:07Z</updated>
<author>
<name>Sami Tolvanen</name>
<email>samitolvanen@google.com</email>
</author>
<published>2023-09-27T22:48:01Z</published>
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<id>urn:sha1:e609b4f4252a2ad2454736078693571b9fbff019</id>
<content type='text'>
In Clang 17, -fsanitize=shadow-call-stack uses the newly declared
platform register gp for storing shadow call stack pointers. As
this is obviously incompatible with gp relaxation, in preparation
for CONFIG_SHADOW_CALL_STACK support, move global pointer loading
to a single macro, which we can cleanly disable when SCS is used
instead.

Link: https://reviews.llvm.org/rGaa1d2693c256
Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/a484e843e6eeb51f0cb7b8819e50da6d2444d769
Signed-off-by: Sami Tolvanen &lt;samitolvanen@google.com&gt;
Tested-by: Nathan Chancellor &lt;nathan@kernel.org&gt;
Link: https://lore.kernel.org/r/20230927224757.1154247-11-samitolvanen@google.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>riscv: Add types to indirectly called assembly functions</title>
<updated>2023-08-23T21:16:37Z</updated>
<author>
<name>Sami Tolvanen</name>
<email>samitolvanen@google.com</email>
</author>
<published>2023-07-10T18:35:47Z</published>
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<id>urn:sha1:5f59c6855bad1809a4f85ce4db412f9ede45a4a0</id>
<content type='text'>
With CONFIG_CFI_CLANG, assembly functions indirectly called
from C code must be annotated with type identifiers to pass CFI
checking. Use the SYM_TYPED_START macro to add types to the
relevant functions.

Reviewed-by: Kees Cook &lt;keescook@chromium.org&gt;
Tested-by: Nathan Chancellor &lt;nathan@kernel.org&gt;
Signed-off-by: Sami Tolvanen &lt;samitolvanen@google.com&gt;
Link: https://lore.kernel.org/r/20230710183544.999540-10-samitolvanen@google.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: Factor out common code of __cpu_resume_enter()</title>
<updated>2023-04-29T18:25:11Z</updated>
<author>
<name>Sia Jee Heng</name>
<email>jeeheng.sia@starfivetech.com</email>
</author>
<published>2023-03-30T06:43:19Z</published>
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<id>urn:sha1:fcb89863d1b798565db6bdaf8f97f65823c2fd1b</id>
<content type='text'>
The cpu_resume() function is very similar for the suspend to disk and
suspend to ram cases. Factor out the common code into suspend_restore_csrs
macro and suspend_restore_regs macro.

Signed-off-by: Sia Jee Heng &lt;jeeheng.sia@starfivetech.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20230330064321.1008373-3-jeeheng.sia@starfivetech.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: Split out the XIP fixups into their own file</title>
<updated>2022-05-25T21:43:33Z</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@rivosinc.com</email>
</author>
<published>2022-04-20T03:02:16Z</published>
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<id>urn:sha1:e7681beba992d5a196476d5d79dfcb48f2a2c477</id>
<content type='text'>
This was broken by the original refactoring (as the XIP definitions
depend on &lt;asm/pgtable.h&gt;) and then more broken by the merge (as I
accidentally took the old version).  This fixes both breakages, while
also pulling this out of &lt;asm/asm.h&gt; to avoid polluting most assembly
files with the XIP fixups.

Fixes: bee7fbc38579 ("RISC-V CPU Idle Support")
Fixes: 63b13e64a829 ("RISC-V: Add arch functions for non-retentive suspend entry/exit")
Link: https://lore.kernel.org/r/20220420184056.7886-4-palmer@rivosinc.com
Reviewed-by: Guo Ren &lt;guoren@kernel.org&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: Add arch functions for non-retentive suspend entry/exit</title>
<updated>2022-03-10T17:29:31Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2022-02-10T05:49:42Z</published>
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<id>urn:sha1:63b13e64a829e7b12fba81fccbea0d5448fc0c24</id>
<content type='text'>
The hart registers and CSRs are not preserved in non-retentative
suspend state so we provide arch specific helper functions which
will save/restore hart context upon entry/exit to non-retentive
suspend state. These helper functions can be used by cpuidle
drivers for non-retentive suspend entry/exit.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Guo Ren &lt;guoren@kernel.org&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
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