<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/arch/sh/include/cpu-sh3/cpu, branch v3.0</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v3.0</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v3.0'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2010-10-06T17:57:39Z</updated>
<entry>
<title>sh: Fix up the SH-3 build.</title>
<updated>2010-10-06T17:57:39Z</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2010-10-06T17:57:39Z</published>
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<id>urn:sha1:06c7a489a97fce99fd86611f6f32e565e686e5d8</id>
<content type='text'>
SH-3 lacks an MMUCR_TI definition for global TLB flushes. As SH-3 parts
lack a split TLB, the same global flush behaviour is accomplished
through the flush bit, which just happens to be the same as on SH-4.

This fixes up the build for all SH-3 MMU parts.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>dmaengine: shdma: separate DMA headers.</title>
<updated>2010-03-02T02:09:04Z</updated>
<author>
<name>Guennadi Liakhovetski</name>
<email>g.liakhovetski@gmx.de</email>
</author>
<published>2010-02-11T16:50:14Z</published>
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<id>urn:sha1:8b1935e6a36b0967efc593d67ed3aebbfbc1f5b1</id>
<content type='text'>
Separate SH DMA headers into ones, commonly used by both drivers, and ones,
specific to each of them. This will make the future development of the
dmaengine driver easier.

Signed-off-by: Guennadi Liakhovetski &lt;g.liakhovetski@gmx.de&gt;
Acked-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'sh/dmaengine'</title>
<updated>2010-02-08T02:34:03Z</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2010-02-08T02:34:03Z</published>
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<id>urn:sha1:2e18e047981ae04be9bd0d9760057f7c1a7b3785</id>
<content type='text'>
Conflicts:
	arch/sh/drivers/dma/dma-sh.c
</content>
</entry>
<entry>
<title>sh: fix Transfer Size calculation in both DMA drivers</title>
<updated>2010-02-08T00:40:24Z</updated>
<author>
<name>Guennadi Liakhovetski</name>
<email>g.liakhovetski@gmx.de</email>
</author>
<published>2010-02-03T14:44:12Z</published>
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<id>urn:sha1:623b4ac4bf9e767991c66e29b47dd4b19458fb42</id>
<content type='text'>
Both the original arch/sh/drivers/dma/dma-sh.c and the new SH dmaengine drivers
do not take into account bits 3:2 of the Transfer Size field in the CHCR
register, besides, bit-field defines set bit 2, but the mask only passes bits
1:0 through. TS_16BLK and TS_32BLK macros are bogus too. This patch fixes all
these issues for sh7722 and sh7724, other CPUs stay unchanged and might need to
be fixed too.

Signed-off-by: Guennadi Liakhovetski &lt;g.liakhovetski@gmx.de&gt;
Acked-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Mass ctrl_in/outX to __raw_read/writeX conversion.</title>
<updated>2010-01-26T03:58:40Z</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2010-01-26T03:58:40Z</published>
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<id>urn:sha1:9d56dd3b083a3bec56e9da35ce07baca81030b03</id>
<content type='text'>
The old ctrl in/out routines are non-portable and unsuitable for
cross-platform use. While drivers/sh has already been sanitized, there
is still quite a lot of code that is not. This converts the arch/sh/ bits
over, which permits us to flag the routines as deprecated whilst still
building with -Werror for the architecture code, and to ensure that
future users are not added.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Kill off dead UBC headers.</title>
<updated>2010-01-05T10:16:35Z</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2010-01-05T10:16:35Z</published>
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<id>urn:sha1:7025bec9125b0a02edcaf22c2dce753bf2c95480</id>
<content type='text'>
Nothing is using these now, so kill them all off.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Convert SH7705 extended mode to new cacheflush interface.</title>
<updated>2009-08-15T03:53:39Z</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2009-08-15T03:53:39Z</published>
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<id>urn:sha1:0d051d90bb08b516b9d6c30d25f83d3c6b5b1c1d</id>
<content type='text'>
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Kill off unused flush_icache_user_range().</title>
<updated>2009-08-15T02:38:05Z</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2009-08-15T02:38:05Z</published>
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<id>urn:sha1:916e97834e023f89b31f796b53cc9c7956e7fe17</id>
<content type='text'>
We use flush_cache_page() outright in copy_to_user_page(), and nothing
else needs it, so just kill it off. SH-5 still defines its own version,
but that too will go away in the same fashion once it converts over.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: consolidate flush_dcache_mmap_lock/unlock() definitions.</title>
<updated>2009-08-15T02:25:32Z</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2009-08-15T02:25:32Z</published>
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<id>urn:sha1:7fbb2d3bdd33e58f54e360df0723d754f0b66153</id>
<content type='text'>
All of the flush_dcache_mmap_lock()/flush_dcache_mmap_unlock()
definitions are identical across all CPUs, so just provide them
generically in asm/cacheflush.h.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Centralize the CPU cache initialization routines.</title>
<updated>2009-08-15T02:05:42Z</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2009-08-15T02:05:42Z</published>
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<id>urn:sha1:ecba1060583635ab55092072441ff903b5e9a659</id>
<content type='text'>
This provides a central point for CPU cache initialization routines.
This replaces the antiquated p3_cache_init() method, which the vast
majority of CPUs never cared about.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
</feed>
