<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/arch/tile/include, branch v3.6</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v3.6</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v3.6'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2012-09-24T19:11:53Z</updated>
<entry>
<title>tile: gxio iorpc numbering change for TRIO interface</title>
<updated>2012-09-24T19:11:53Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2012-09-24T18:57:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e70cf54073acb6494620620af2ab993d57ae8d3f'/>
<id>urn:sha1:e70cf54073acb6494620620af2ab993d57ae8d3f</id>
<content type='text'>
An ABI numbering change was made in the hypervisor for Tilera's 4.1
MDE release (just shipped).  It's incompatible with the previous 4.0
release ABI numbering, so we track the new numbering going forward.
We plan to avoid modifying ABI numbering for these interfaces again.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'trivial' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild</title>
<updated>2012-07-30T18:24:53Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2012-07-30T18:24:53Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=637e49ae4f5b4a82b418dae8435e16132b298b7e'/>
<id>urn:sha1:637e49ae4f5b4a82b418dae8435e16132b298b7e</id>
<content type='text'>
Pull treewide kbuild cleanup from Michal Marek:
 "Paul Bolle did a cleanup of &lt;asm/*.h&gt; headers in various
  architectures.  Because the patch touch several architectures at
  once, it was easiest for me to apply them to the kbuild tree."

* 'trivial' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild:
  Remove useless wrappers of asm-generic/rmap.h
  Remove useless wrappers of asm-generic/ipc.h
  Remove useless wrappers of asm-generic/cpumask.h
</content>
</entry>
<entry>
<title>Merge branch 'kmap_atomic' of git://github.com/congwang/linux</title>
<updated>2012-07-27T18:26:48Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2012-07-27T18:26:48Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=84eda28060f7e7d5f91f81f928532af13b9e44b2'/>
<id>urn:sha1:84eda28060f7e7d5f91f81f928532af13b9e44b2</id>
<content type='text'>
Pull final kmap_atomic cleanups from Cong Wang:
 "This should be the final round of cleanup, as the definitions of enum
  km_type finally get removed from the whole tree.  The patches have
  been in linux-next for a long time."

* 'kmap_atomic' of git://github.com/congwang/linux:
  pipe: remove KM_USER0 from comments
  vmalloc: remove KM_USER0 from comments
  feature-removal-schedule.txt: remove kmap_atomic(page, km_type)
  tile: remove km_type definitions
  um: remove km_type definitions
  asm-generic: remove km_type definitions
  avr32: remove km_type definitions
  frv: remove km_type definitions
  powerpc: remove km_type definitions
  arm: remove km_type definitions
  highmem: remove the deprecated form of kmap_atomic
  tile: remove usage of enum km_type
  frv: remove the second parameter of kmap_atomic_primary()
  jbd2: remove the second argument of kmap_atomic
</content>
</entry>
<entry>
<title>tile: remove km_type definitions</title>
<updated>2012-07-24T07:27:32Z</updated>
<author>
<name>Cong Wang</name>
<email>amwang@redhat.com</email>
</author>
<published>2011-11-25T14:57:35Z</published>
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<id>urn:sha1:ecee6f9bd4e97993ede4f97cf922fc4bf4264c04</id>
<content type='text'>
Signed-off-by: Cong Wang &lt;amwang@redhat.com&gt;
</content>
</entry>
<entry>
<title>tile: updates to pci root complex from community feedback</title>
<updated>2012-07-18T20:54:16Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2012-07-18T16:06:19Z</published>
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<id>urn:sha1:f6d2ce00da145ae31ec22d21daca6ca5e22b3c84</id>
<content type='text'>
Reviewed-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>arch/tile: provide kernel support for the tilegx USB shim</title>
<updated>2012-07-18T20:40:24Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2012-05-09T16:25:02Z</published>
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<id>urn:sha1:d1cc1732cc62034542b042a4506d7c5043bc5e5e</id>
<content type='text'>
This change adds support for accessing the USB shim from within the
kernel.  Note that this change by itself does not allow the kernel
to act as a host or as a device; it merely exposes the built-in on-chip
hardware to the kernel.

The &lt;arch/usb_host.h&gt; and &lt;arch/usb_host_def.h&gt; headers are empty at
the moment because the kernel does not require any types or definitions
specific to the tilegx USB shim; the generic USB core code is all we need.
The headers are left in as stubs so that we don't need to modify the
hypervisor header (drv_usb_host_intf.h) from upstream.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile pci: enable IOMMU to support DMA for legacy devices</title>
<updated>2012-07-18T20:40:17Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2012-06-15T19:23:06Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=41bb38fc5398ae878c799647f3c4b25374029afb'/>
<id>urn:sha1:41bb38fc5398ae878c799647f3c4b25374029afb</id>
<content type='text'>
This change uses the TRIO IOMMU to map the PCI DMA space and physical
memory at different addresses.  We also now use the dma_mapping_ops
to provide support for non-PCI DMA, PCIe DMA (64-bit) and legacy PCI
DMA (32-bit).  We use the kernel's software I/O TLB framework
(i.e. bounce buffers) for the legacy 32-bit PCI device support since
there are a limited number of TLB entries in the IOMMU and it is
non-trivial to handle indexing, searching, matching, etc.  For 32-bit
devices the performance impact of bounce buffers should not be a concern.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tilegx pci: support I/O to arbitrarily-cached pages</title>
<updated>2012-07-18T20:40:05Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2012-06-13T18:46:40Z</published>
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<id>urn:sha1:bbaa22c3a0d0be4406d26e5a73d1e8e504787986</id>
<content type='text'>
The tilegx PCI root complex support (currently only in linux-next)
is limited to pages that are homed on cached in the default manner,
i.e. "hash-for-home".  This change supports delivery of I/O data to
pages that are cached in other ways (locally on a particular core,
uncached, user-managed incoherent, etc.).

A large part of the change is supporting flushing pages from cache
on particular homes so that we can transition the data that we are
delivering to or from the device appropriately.  The new homecache_finv*
routines handle this.

Some changes to page_table_range_init() were also required to make
the fixmap code work correctly on tilegx; it hadn't been used there
before.

We also remove some stub mark_caches_evicted_*() routines that
were just no-ops anyway.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>tile: remove unused header</title>
<updated>2012-07-18T20:40:00Z</updated>
<author>
<name>Paul Bolle</name>
<email>pebolle@tiscali.nl</email>
</author>
<published>2012-06-10T19:44:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=3e219b91533058e242b78ac08aaa91024dd6f369'/>
<id>urn:sha1:3e219b91533058e242b78ac08aaa91024dd6f369</id>
<content type='text'>
Nothing includes memprof.h. Nothing uses the macros it defines. It seems
it is just a remnant of the proposed memprof functionality, which got
dropped before the Tilera architecture got added to the tree. This
header can safely be removed.

Signed-off-by: Paul Bolle &lt;pebolle@tiscali.nl&gt;
Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>arch/tile: tilegx PCI root complex support</title>
<updated>2012-07-18T20:39:11Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2012-04-07T21:10:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=129622672d70711c6c844fb529381ff0dad9085a'/>
<id>urn:sha1:129622672d70711c6c844fb529381ff0dad9085a</id>
<content type='text'>
This change implements PCIe root complex support for tilegx using
the kernel support layer for accessing the TRIO hardware shim.

Reviewed-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt; [changes in 07487f3]
Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
</feed>
