<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/arch/tile/kernel, branch v2.6.37</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v2.6.37</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v2.6.37'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2010-12-17T21:59:29Z</updated>
<entry>
<title>arch/tile: handle rt_sigreturn() more cleanly</title>
<updated>2010-12-17T21:59:29Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2010-12-14T21:07:25Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=81711cee933599fa114abb0d258d8bbabef8adfb'/>
<id>urn:sha1:81711cee933599fa114abb0d258d8bbabef8adfb</id>
<content type='text'>
The current tile rt_sigreturn() syscall pattern uses the common idiom
of loading up pt_regs with all the saved registers from the time of
the signal, then anticipating the fact that we will clobber the ABI
"return value" register (r0) as we return from the syscall by setting
the rt_sigreturn return value to whatever random value was in the pt_regs
for r0.

However, this breaks in our 64-bit kernel when running "compat" tasks,
since we always sign-extend the "return value" register to properly
handle returned pointers that are in the upper 2GB of the 32-bit compat
address space.  Doing this to the sigreturn path then causes occasional
random corruption of the 64-bit r0 register.

Instead, we stop doing the crazy "load the return-value register"
hack in sigreturn.  We already have some sigreturn-specific assembly
code that we use to pass the pt_regs pointer to C code.  We extend that
code to also set the link register to point to a spot a few instructions
after the usual syscall return address so we don't clobber the saved r0.
Now it no longer matters what the rt_sigreturn syscall returns, and the
pt_regs structure can be cleanly and completely reloaded.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>arch/tile: handle CLONE_SETTLS in copy_thread(), not user space</title>
<updated>2010-12-17T21:56:50Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2010-12-14T20:57:49Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=bc4cf2bb271b2d557fc510426755da786fc985be'/>
<id>urn:sha1:bc4cf2bb271b2d557fc510426755da786fc985be</id>
<content type='text'>
Previously we were just setting up the "tp" register in the
new task as started by clone() in libc.  However, this is not
quite right, since in principle a signal might be delivered to
the new task before it had its TLS set up.  (Of course, this race
window still exists for resetting the libc getpid() cached value
in the new task, in principle.  But in any case, we are now doing
this exactly the way all other architectures do it.)

This change is important for 2.6.37 since the tile glibc we will
be submitting upstream will not set TLS in user space any more,
so it will only work on a kernel that has this fix.  It should
also be taken for 2.6.36.x in the stable tree if possible.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
Cc: stable &lt;stable@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile</title>
<updated>2010-11-24T22:42:32Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2010-11-24T22:42:32Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c12ae95ccc2dc80b4bd57363240cdb6eab2adcbc'/>
<id>urn:sha1:c12ae95ccc2dc80b4bd57363240cdb6eab2adcbc</id>
<content type='text'>
* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile:
  arch/tile: fix memchr() not to dereference memory for zero length
  arch/tile: make glibc's sysconf(_SC_NPROCESSORS_CONF) work correctly
  arch/tile: fix rwlock so would-be write lockers don't block new readers
</content>
</entry>
<entry>
<title>Merge branch 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile</title>
<updated>2010-11-24T22:42:03Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2010-11-24T22:42:03Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=47143b094d4700842e42b0a7cc2548d7ae292690'/>
<id>urn:sha1:47143b094d4700842e42b0a7cc2548d7ae292690</id>
<content type='text'>
* 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile:
  pci root complex: support for tile architecture
  drivers/net/tile/: on-chip network drivers for the tile architecture
  MAINTAINERS: add drivers/char/hvc_tile.c as maintained by tile
</content>
</entry>
<entry>
<title>arch/tile: make glibc's sysconf(_SC_NPROCESSORS_CONF) work correctly</title>
<updated>2010-11-24T18:42:15Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2010-11-24T18:42:15Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4d658d13c90f14cf3510ca15cafe2f4aa9e23d64'/>
<id>urn:sha1:4d658d13c90f14cf3510ca15cafe2f4aa9e23d64</id>
<content type='text'>
glibc assumes that it can count /sys/devices/system/cpu/cpu* to get
the number of configured cpus.  For this to be valid on tile, we need
to generate a "cpu" entry for all cpus, including the ones that are
not currently allocated for Linux's use.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>pci root complex: support for tile architecture</title>
<updated>2010-11-24T18:13:49Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2010-11-02T16:05:10Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f02cbbe657939489347cbda598401a56913ffcbd'/>
<id>urn:sha1:f02cbbe657939489347cbda598401a56913ffcbd</id>
<content type='text'>
This change enables PCI root complex support for TILEPro.  Unlike
TILE-Gx, TILEPro has no support for memory-mapped I/O, so the PCI
support consists of hypervisor upcalls for PIO, DMA, etc.  However,
the performance is fine for the devices we have tested with so far
(1Gb Ethernet, SATA, etc.).

The &lt;asm/io.h&gt; header was tweaked to be a little bit more aggressive
about disabling attempts to map/unmap IO port space.  The hacky
&lt;asm/pci-bridge.h&gt; header was rolled into the &lt;asm/pci.h&gt; header
and the result was simplified.  Both of the latter two headers were
preliminary versions not meant for release before now - oh well.

There is one quirk for our TILEmpower platform, which accidentally
negotiates up to 5GT and needs to be kicked down to 2.5GT.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>BKL: remove extraneous #include &lt;smp_lock.h&gt;</title>
<updated>2010-11-17T16:59:32Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2010-11-17T15:26:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=451a3c24b0135bce54542009b5fde43846c7cf67'/>
<id>urn:sha1:451a3c24b0135bce54542009b5fde43846c7cf67</id>
<content type='text'>
The big kernel lock has been removed from all these files at some point,
leaving only the #include.

Remove this too as a cleanup.

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>arch/tile: mark "hardwall" device as non-seekable</title>
<updated>2010-11-01T19:31:42Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2010-11-01T16:46:10Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d02db4f8d79c5841ba32b326edb75ea6acd081ca'/>
<id>urn:sha1:d02db4f8d79c5841ba32b326edb75ea6acd081ca</id>
<content type='text'>
Arnd's recent patch series tagged this device with noop_llseek,
conservatively.  In fact, it should be no_llseek, which we arrange
for by opening the device with nonseekable_open().

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
<entry>
<title>asm-generic/stat.h: support 64-bit file time_t for stat()</title>
<updated>2010-11-01T19:31:29Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2010-10-28T20:07:07Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2c7387ef9969bb073c25ecbdcc5be30770267b16'/>
<id>urn:sha1:2c7387ef9969bb073c25ecbdcc5be30770267b16</id>
<content type='text'>
The existing asm-generic/stat.h specifies st_mtime, etc., as a 32-value,
and works well for 32-bit architectures (currently microblaze, score,
and 32-bit tile).  However, for 64-bit architectures it isn't sufficient
to return 32 bits of time_t; this isn't good insurance against the 2037
rollover.  (It also makes glibc support less convenient, since we can't
use glibc's handy STAT_IS_KERNEL_STAT mode.)

This change extends the two "timespec" fields for each of the three atime,
mtime, and ctime fields from "int" to "long".  As a result, on 32-bit
platforms nothing changes, and 64-bit platforms will now work as expected.

The only wrinkle is 32-bit userspace under 64-bit kernels taking advantage
of COMPAT mode.  For these, we leave the "struct stat64" definitions with
the "int" versions of the time_t and nsec fields, so that architectures
can implement compat_sys_stat64() and friends with sys_stat64(), etc.,
and get the expected 32-bit structure layout.  This requires a
field-by-field copy in the kernel, implemented by the code guarded
under __ARCH_WANT_STAT64.

This does mean that the shape of the "struct stat" and "struct stat64"
structures is different on a 64-bit kernel, but only one of the two
structures should ever be used by any given process: "struct stat"
is meant for 64-bit userspace only, and "struct stat64" for 32-bit
userspace only.  (On a 32-bit kernel the two structures continue to have
the same shape, since "long" is 32 bits.)

The alternative is keeping the two structures the same shape on 64-bit
kernels, which means a 64-bit time_t in "struct stat64" for 32-bit
processes.  This is a little unnatural since 32-bit userspace can't
do anything with 64 bits of time_t information, since time_t is just
"long", not "int64_t"; and in any case 32-bit userspace might expect
to be running under a 32-bit kernel, which can't provide the high 32
bits anyway.  In the case of a 32-bit kernel we'd then be extending the
kernel's 32-bit time_t to 64 bits, then truncating it back to 32 bits
again in userspace, for no particular reason.  And, as mentioned above,
if we have 64-bit time_t for 32-bit processes we can't easily use glibc's
STAT_IS_KERNEL_STAT, since glibc's stat structure requires an embedded
"struct timespec", which is a pair of "long" (32-bit) values in a 32-bit
userspace.  "Inventive" solutions are possible, but are pretty hacky.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>arch/tile: don't allow user code to set the PL via ptrace or signal return</title>
<updated>2010-11-01T19:31:17Z</updated>
<author>
<name>Chris Metcalf</name>
<email>cmetcalf@tilera.com</email>
</author>
<published>2010-10-28T19:47:06Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1deb9c5dfb179819ecdbf80a1d121e26c63caab3'/>
<id>urn:sha1:1deb9c5dfb179819ecdbf80a1d121e26c63caab3</id>
<content type='text'>
The kernel was allowing any component of the pt_regs to be updated either
by signal handlers writing to the stack, or by processes writing via
PTRACE_POKEUSR or PTRACE_SETREGS, which meant they could set their PL
up from 0 to 1 and get access to kernel code and data (or, in practice,
cause a kernel panic).  We now always reset the ex1 field, allowing the
user to set their ICS bit only.

Signed-off-by: Chris Metcalf &lt;cmetcalf@tilera.com&gt;
</content>
</entry>
</feed>
