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<title>linux/arch/xtensa/boot, branch v4.9</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.9</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.9'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2016-09-21T01:52:59Z</updated>
<entry>
<title>xtensa: rearrange CCOUNT calibration</title>
<updated>2016-09-21T01:52:59Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2016-09-20T18:11:08Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=205ad548a7426fb6813760cd9917d3fc24122576'/>
<id>urn:sha1:205ad548a7426fb6813760cd9917d3fc24122576</id>
<content type='text'>
DT-enabled kernel should have a CPU node connected to a clock. This clock
is the CCOUNT clock. Use old platform_calibrate_ccount call as a fallback
when CPU node cannot be found or has no clock and in non-DT-enabled
configurations.

Drop no longer needed code that updates CPU clock-frequency property in
the DT; drop DT-related code from the platform_calibrate_ccount too.

Move of_clk_init to the top of time_init, so that clocks are initialized
before CCOUNT calibration is attempted.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: xtfpga: use clock provider, don't update DT</title>
<updated>2016-09-21T01:52:51Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2016-07-25T07:58:10Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=58c3e3ac7a1daf56523567507a096a3e4026596d'/>
<id>urn:sha1:58c3e3ac7a1daf56523567507a096a3e4026596d</id>
<content type='text'>
Instead of querying hardcoded FPGA frequency register and then updating
clock-frequency property in specificly named DT nodes in machine setup
code register a clock provider that returns fixed-rate clock, configured
by register specified in DT. This way we have less magic/hardcoded names
and use more existing common clock framework code.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Tested-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
</content>
</entry>
<entry>
<title>xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config.</title>
<updated>2016-09-19T18:51:32Z</updated>
<author>
<name>Scott Telford</name>
<email>stelford@cadence.com</email>
</author>
<published>2016-09-15T15:26:45Z</published>
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<id>urn:sha1:bebbc4bcf36f015a5a051cc8817b11de209fbe8b</id>
<content type='text'>
Add module parameter xilinx_uartps.rx_trigger_level=32 to command line
options for CSP to set Rx watermark for xuartps driver lower than the
default value, to avoid UART overruns at 115200 bps.

Signed-off-by: Scott Telford &lt;stelford@cadence.com&gt;
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: Added Cadence CSP kernel configuration for Xtensa</title>
<updated>2016-09-10T01:39:09Z</updated>
<author>
<name>Scott Telford</name>
<email>stelford@cadence.com</email>
</author>
<published>2016-09-08T15:41:24Z</published>
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<id>urn:sha1:23c2b9321b30f947b4f908e40379eed50f48508c</id>
<content type='text'>
Added defconfig, device tree and Xtensa variant header files for the
Cadence Configurable System Platform "xt_lnx" processor configuration.

Signed-off-by: Scott Telford &lt;stelford@cadence.com&gt;
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: cleanup MMU setup and kernel layout macros</title>
<updated>2016-07-24T03:33:58Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2016-04-13T02:20:02Z</published>
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<id>urn:sha1:a9f2fc628e3a26a829fd79aff74eb49839d1e74b</id>
<content type='text'>
Make kernel load address explicit, independent of the selected MMU
configuration and configurable from Kconfig. Do not restrict it to the
first 512MB of the physical address space.

Cleanup kernel memory layout macros:

- rename VECBASE_RESET_VADDR to VECBASE_VADDR, XC_VADDR to VECTOR_VADDR;
- drop VIRTUAL_MEMORY_ADDRESS and LOAD_MEMORY_ADDRESS;
- introduce PHYS_OFFSET and use it in __va and __pa definitions;
- synchronize MMU/noMMU vectors, drop unused NMI vector;
- replace hardcoded vectors offset of 0x3000 with Kconfig symbol.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: xtfpga: fix earlycon endianness</title>
<updated>2016-03-11T08:53:32Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2015-09-22T11:19:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=56b9f9d672fe373093b764cf046da7c7d3737bda'/>
<id>urn:sha1:56b9f9d672fe373093b764cf046da7c7d3737bda</id>
<content type='text'>
Serial port is attached to XTFPGA boards as native endian device, now
that earlycon parameter parser understands mmio32native put it into
earlycon kernel parameter. This makes early console functional on both
little- and big-endian CPUs with identical kernel command lines.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: xtfpga: fix i2c controller register width and endianness</title>
<updated>2016-03-11T08:53:32Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2015-08-25T15:19:13Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=bce299ca54735740a4f2232d23001dea679fbbef'/>
<id>urn:sha1:bce299ca54735740a4f2232d23001dea679fbbef</id>
<content type='text'>
I2C controller is attached to XTFPGA boards as native endian device, mark
it as such in DTS.
Set register width in DTS to 4, this way it works both for little- and
big-endian CPUs.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: xtfpga: fix ethernet controller endianness</title>
<updated>2016-03-11T08:53:31Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2015-08-25T06:04:12Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d99434e1760b94e08512821b5a05992398c1aa9e'/>
<id>urn:sha1:d99434e1760b94e08512821b5a05992398c1aa9e</id>
<content type='text'>
Ethernet controller is attached to XTFPGA boards as native endian device,
mark it as such in DTS and pass correct endianness in platform data.
This makes network functional on big-endian CPUs.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: xtfpga: fix serial port register width and endianness</title>
<updated>2016-03-11T08:53:31Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2015-08-24T16:44:46Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=abfbd89595e91d5108f807e10bbd2152bc55f36b'/>
<id>urn:sha1:abfbd89595e91d5108f807e10bbd2152bc55f36b</id>
<content type='text'>
Serial port is attached to XTFPGA boards as native endian device, mark
it as such in DTS and pass correct endianness in platform data.
Set register width in DTS to 4, this way it matches the platform data
and works correctly on big-endian CPUs.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'xtensa-20151108' of git://github.com/czankel/xtensa-linux</title>
<updated>2015-11-10T00:32:13Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2015-11-10T00:32:13Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=3510ca19a82ba4c6a17af79c1f0448622a406efa'/>
<id>urn:sha1:3510ca19a82ba4c6a17af79c1f0448622a406efa</id>
<content type='text'>
Pull xtensa updates from Chris Zankel:

 - fix remaining issues with noMMU cores
 - fix build for cores w/o cache or zero overhead loop options
 - fix boot of secondary cores in SMP configuration
 - add support for DMA to high memory pages
 - add dma_to_phys and phys_to_dma functions.

* tag 'xtensa-20151108' of git://github.com/czankel/xtensa-linux:
  xtensa: implement dma_to_phys and phys_to_dma
  xtensa: support DMA to high memory
  Revert "xtensa: cache inquiry and unaligned cache handling functions"
  xtensa: drop unused sections and remapped reset handlers
  xtensa: fix secondary core boot in SMP
  xtensa: add FORCE_MAX_ZONEORDER to Kconfig
  xtensa: nommu: provide defconfig for de212 on kc705
  xtensa: nommu: xtfpga: add kc705 DTS
  xtensa: add de212 core variant
  xtensa: nommu: select HAVE_FUTEX_CMPXCHG
  xtensa: nommu: fix default memory start address
  xtensa: nommu: provide correct KIO addresses
  xtensa: nommu: fix USER_RING definition
  xtensa: xtfpga: fix integer overflow in TASK_SIZE
  xtensa: fix build for configs without cache options
  xtensa: fixes for configs without loop option
</content>
</entry>
</feed>
