linux/arch/xtensa/kernel/Makefile, branch v4.9

xtensa: support hardware breakpoints/watchpoints

2016-03-11T08:53:32Z

Use perf framework to manage hardware instruction and data breakpoints. Add two new ptrace calls: PTRACE_GETHBPREGS and PTRACE_SETHBPREGS to query and set instruction and data breakpoints. Address bit 0 choose instruction (0) or data (1) break register, bits 31..1 are the register number. Both calls transfer two 32-bit words: address (0) and control (1). Instruction breakpoint contorl word is 0 to clear breakpoint, 1 to set. Data breakpoint control word bit 31 is 'trigger on store', bit 30 is 'trigger on load, bits 29..0 are length. Length 0 is used to clear a breakpoint. To set a breakpoint length must be a power of 2 in the range 1..64 and the address must be length-aligned. Introduce new thread_info flag: TIF_DB_DISABLED. Set it if debug exception is raised by the kernel code accessing watched userspace address and disable corresponding data breakpoint. On exit to userspace check that flag and, if set, restore all data breakpoints. Handle debug exceptions raised with PS.EXCM set. This may happen when window overflow/underflow handler or fast exception handler hits data breakpoint, in which case save and disable all data breakpoints, single-step faulting instruction and restore data breakpoints. Signed-off-by: Max Filippov

xtensa: remove remaining non-functional KGDB bits

2016-03-11T08:53:32Z

KGDB is not supported on xtensa, but there are bits of related code under arch/xtensa/kernel. Remove these bits. Signed-off-by: Max Filippov

xtensa: fix secondary core boot in SMP

2015-11-03T14:19:38Z

There are multiple factors adding to the issue in different configurations: - commit 17290231df16eeee ("xtensa: add fixup for double exception raised in window overflow") added function window_overflow_restore_a0_fixup to double exception vector overlapping reset vector location of secondary processor cores. - on MMUv2 cores RESET_VECTOR1_VADDR may point to uncached kernel memory making code overlapping depend on cache type and size, so that without cache or with WT cache reset vector code overwrites double exception code, making issue even harder to detect. - on MMUv3 cores RESET_VECTOR1_VADDR may point to unmapped area, as MMUv3 cores change virtual address map to match MMUv2 layout, but reset vector virtual address is given for the original MMUv3 mapping. - physical memory region of the secondary reset vector is not reserved in the physical memory map, and thus may be allocated and overwritten at arbitrary moment. Fix it as follows: - move window_overflow_restore_a0_fixup code to .text section. - define RESET_VECTOR1_VADDR so that it points to reset vector in the cacheable MMUv2 map for cores with MMU. - reserve reset vector region in the physical memory map. Drop separate literal section and build mxhead.S with text section literals. Cc: Signed-off-by: Max Filippov

xtensa: improve vmlinux.lds.S sed post-processing

2015-08-20T15:28:42Z

Current sed script makes assumptions about the structure of rules that group .text sections in the vmlinux linker script. These assumptions get broken occasionally, e.g.: 779c88c94c34 "ARM: 8321/1: asm-generic: introduce.text.fixup input section", or 9bebe9e5b0f3 "kbuild: Fix .text.unlikely placement". Rewrite sed rules so that they don't depend on number/arrangement of text sections in *(...) blocks. Signed-off-by: Max Filippov

xtensa: implement counting and sampling perf events

2015-08-17T04:33:30Z

Xtensa Performance Monitor Module has up to 8 32 bit wide performance counters. Each counter may be enabled independently and can count any single type of hardware performance events. Event counting may be enabled and disabled globally (per PMM). Each counter has status register with bits indicating if the counter has been overflown and may be programmed to raise profiling IRQ on overflow. This IRQ is used to rewind counters and allow for counting more than 2^32 samples for counting events and to report samples for sampling events. For more details see Tensilica Debug User's Guide, chapter 8 "Performance monitor module". Cc: Peter Zijlstra Cc: Paul Mackerras Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Signed-off-by: Max Filippov

xtensa: Fix fix linker script transformation for .text / .text.fixup

2015-04-10T07:31:21Z

Commit 779c88c94c34 ("ARM: 8321/1: asm-generic: introduce .text.fixup input section") introduced a new .text.fixup section which is merged with .text at link time. This causes xtensa builds to fail with lots of error messages similar to the following. lib/lib.a(kobject.o): In function `kobject_create': (.text+0x498): dangerous relocation: l32r: literal placed after use: (.literal+0x150) Linker script transformation needs to be updated to detect and handle the new section. Fixes: 779c88c94c34 ("ARM: 8321/1: asm-generic: introduce .text.fixup input section") Cc: Ard Biesheuvel Cc: Arnd Bergmann Signed-off-by: Guenter Roeck Signed-off-by: Chris Zankel

xtensa: add SMP support

2014-01-14T18:19:58Z

This is largely based on SMP code from the xtensa-2.6.29-smp tree by Piet Delaney, Marc Gauthier, Joe Taylor, Christian Zankel (and possibly other Tensilica folks). Signed-off-by: Max Filippov Signed-off-by: Chris Zankel

xtensa: add static function tracer support

2013-07-08T08:18:57Z

Signed-off-by: Max Filippov Signed-off-by: Chris Zankel

xtensa: add stacktrace support

2013-05-09T08:07:10Z

Signed-off-by: Max Filippov Signed-off-by: Chris Zankel

xtensa: add MMU v3 support

2013-05-09T08:07:09Z

MMUv3 comes out of reset with identity vaddr -> paddr mapping in the TLB way 6: Way 6 (512 MB) Vaddr Paddr ASID Attr RWX Cache ---------- ---------- ---- ---- --- ------- 0x00000000 0x00000000 0x01 0x03 RWX Bypass 0x20000000 0x20000000 0x01 0x03 RWX Bypass 0x40000000 0x40000000 0x01 0x03 RWX Bypass 0x60000000 0x60000000 0x01 0x03 RWX Bypass 0x80000000 0x80000000 0x01 0x03 RWX Bypass 0xa0000000 0xa0000000 0x01 0x03 RWX Bypass 0xc0000000 0xc0000000 0x01 0x03 RWX Bypass 0xe0000000 0xe0000000 0x01 0x03 RWX Bypass This patch adds remapping code at the reset vector or at the kernel _start (depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) that reconfigures MMUv3 as MMUv2: Way 5 (128 MB) Vaddr Paddr ASID Attr RWX Cache ---------- ---------- ---- ---- --- ------- 0xd0000000 0x00000000 0x01 0x07 RWX WB 0xd8000000 0x00000000 0x01 0x03 RWX Bypass Way 6 (256 MB) Vaddr Paddr ASID Attr RWX Cache ---------- ---------- ---- ---- --- ------- 0xe0000000 0xf0000000 0x01 0x07 RWX WB 0xf0000000 0xf0000000 0x01 0x03 RWX Bypass Signed-off-by: Max Filippov Signed-off-by: Chris Zankel