linux/arch, branch v3.18

Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2014-12-05T18:47:19Z

Pull x86 fixes from Thomas Gleixner: "Two final fixlets for 3.18: - Prevent microcode reload wreckage on 32bit - Unbreak cross compilation" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86, microcode: Limit the microcode reloading to 64-bit for now x86: Use $(OBJDUMP) instead of plain objdump

s390: fix machine check handling

2014-12-01T10:06:55Z

Commit eb7e7d76 "s390: Replace __get_cpu_var uses" broke machine check handling. We copy machine check information from per-cpu to a stack variable for local processing. Next we should zap the per-cpu variable, not the stack variable. Signed-off-by: Sebastian Ott Reviewed-by: Heiko Carstens Acked-by: Christoph Lameter Signed-off-by: Martin Schwidefsky

x86, microcode: Limit the microcode reloading to 64-bit for now

2014-12-01T09:55:08Z

First, there was this: https://bugzilla.kernel.org/show_bug.cgi?id=88001 The problem there was that microcode patches are not being reapplied after suspend-to-ram. It was important to reapply them, though, because of for example Haswell's TSX erratum which disabled TSX instructions with a microcode patch. A simple fix was fb86b97300d9 ("x86, microcode: Update BSPs microcode on resume") but, as it is often the case, simple fixes are too simple. This one causes 32-bit resume to fail: https://bugzilla.kernel.org/show_bug.cgi?id=88391 Properly fixing this would require more involved changes for which it is too late now, right before the merge window. Thus, limit this to 64-bit only temporarily. Signed-off-by: Borislav Petkov Link: http://lkml.kernel.org/r/1417353999-32236-1-git-send-email-bp@alien8.de Signed-off-by: Thomas Gleixner

Merge tag 'armsoc-for-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

2014-11-28T21:34:32Z

Pull ARM SoC fixes from Arnd Bergmann: "Not much interesting going on fixes-wise for us this week, as it should be for an -rc7. I'm not expecting Olof to work much over Thanksgiving weekend, so I decided to take over again and push these out to you. Just four simple fixes this week: - one missing of_node_put() on armv7 based mvebu - forcing the USB host into the right mode on Chromebook (exynos5-snow) - enabling two important drivers for exynos_defconfig - fixing a noncritical bug for tegra that would cause a regression with common code patches queued for 3.19" * tag 'armsoc-for-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: tegra: irq: fix buggy usage of irq_data irq field ARM: exynos_defconfig: Enable max77802 rtc and clock drivers ARM: dts: Explicitly set dr_mode on exynos5250-snow ARM: mvebu: add missing of_node_put() call in coherency.c

Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm

2014-11-28T21:32:47Z

Pull ARM fixes from Russell King: "Another round of relatively small ARM fixes. Thomas spotted that the strex backoff delay bit was a disable bit, so it needed to be clear for this to work. Vladimir spotted that using a restart block for the cache flush operation would return -EINTR, which userspace was not expecting. Dmitry spotted that the auxiliary control register accesses for Xscale were not correct" * 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: ARM: 8226/1: cacheflush: get rid of restarting block ARM: 8222/1: mvebu: enable strex backoff delay ARM: 8216/1: xscale: correct auxiliary register in suspend/resume

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

2014-11-28T02:32:49Z

Pull mips fixes from Ralf Baechle: "The hopefully final round of fixes for 3.18: - Fix a number of build errors affecting particular configurations. - Handle EVA correctly when flushing a signal trampoline and dcache lines. - Fix printks printing jibberish. - Handle 64 bit memory addresses correctly when adding memory chunk on 32 bit kernels. - Fix a race condition in the hardware tablewalker code" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: tlbex: Fix potential HTW race on TLBL/M/S handlers MIPS: Fix address type used for early memory detection. MIPS: Kconfig: Don't allow both microMIPS and SmartMIPS to be selected. MIPS: kernel: cps-vec: Set ISA level to mips32r2 for the MIPS MT ASE MIPS: Netlogic: handle modular AHCI builds MIPS: Netlogic: handle modular USB case MIPS: Loongson: Make platform serial setup always built-in. MIPS: fix EVA & non-SMP non-FPU FP context signal handling MIPS: cpu-probe: Set the FTLB probability bit on supported cores MIPS: BMIPS: Fix ".previous without corresponding .section" warnings MIPS: uaccess.h: Fix strnlen_user comment. MIPS: r4kcache: Add EVA case for protected_writeback_dcache_line MIPS: Fix info about plat_setup in arch_mem_init comment MIPS: rtlx: Remove KERN_DEBUG from pr_debug() arguments in rtlx.c MIPS: SEAD3: Fix LED device registration. MIPS: Fix a copy & paste error in unistd.h

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux

2014-11-28T02:23:41Z

Pull powerpc fixes from Michael Ellerman: "Here are five fixes for you to pull please. They're all CC'ed to stable except the "Fix PE state format" one which went in this release" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux: powerpc: 32 bit getcpu VDSO function uses 64 bit instructions powerpc/powernv: Replace OPAL_DEASSERT_RESET with EEH_RESET_DEACTIVATE powerpc/eeh: Fix PE state format powerpc/pseries: Fix endiannes issue in RTAS call from xmon powerpc/powernv: Fix the hmi event version check.

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc

2014-11-28T02:19:25Z

Pull sparc fixlet from David Miller: "Aparc fix to add dma_cache_sync(), even if a nop it should be provided if dma_{alloc,free}_noncoherent() is provided too" * git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc: sparc: Add NOP dma_cache_sync() implementation.

MIPS: tlbex: Fix potential HTW race on TLBL/M/S handlers

2014-11-27T16:21:56Z

There is a potential race when probing the TLB in TLBL/M/S exception handlers for a matching entry. Between the time we hit a TLBL/S/M exception and the time we get to execute the TLBP instruction, the HTW may have replaced the TLB entry we are interested in hence the TLB probe may fail. However, in the existing handlers, we never checked the status of the TLBP (ie check the result in the C0/Index register). We fix this by adding such a check when the core implements the HTW. If we couldn't find a matching entry, we return back and try again. Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras Reviewed-by: James Hogan Cc: # v3.17+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8599/ Signed-off-by: Ralf Baechle

ARM: 8226/1: cacheflush: get rid of restarting block

2014-11-27T15:55:35Z

We cannot restart cacheflush safely if a process provides user-defined signal handler and signal is pending. In this case -EINTR is returned and it is expected that process re-invokes syscall. However, there are a few problems with that: * looks like nobody bothers checking return value from cacheflush * but if it did, we don't provide the restart address for that, so the process has to use the same range again * ...and again, what might lead to looping forever So, remove cacheflush restarting code and terminate cache flushing as early as fatal signal is pending. Cc: stable@vger.kernel.org # 3.12+ Reported-by: Chanho Min Signed-off-by: Vladimir Murzin Acked-by: Will Deacon Signed-off-by: Russell King