linux/drivers/accel/habanalabs/include, branch master

accel/habanalbs/gaudi2: reduce interrupt count to 128

2024-06-23T06:53:07Z

Some systems allow a maximum number of 128 MSI-X interrupts. Hence we reduce the interrupt count to 128 instead of 512. Reviewed-by: Tomer Tayar Signed-off-by: Ofir Bitton

accel/habanalabs/gaudi2: add GAUDI2D revision support

2024-06-23T06:53:04Z

Gaudi2 with PCI revision ID with the value of '4' represents Gaudi2D device and should be detected and initialized as Gaudi2. Signed-off-by: Farah Kassabri Reviewed-by: Ofir Bitton Signed-off-by: Ofir Bitton

accel/habanalabs/gaudi2: align interrupt names to table

2024-06-23T06:53:03Z

when reporting tpc events, the dcore and tpc in dcore should be reported and propagated, and not the generatl tpc number Signed-off-by: Ariel Suller Reviewed-by: Ofir Bitton Signed-off-by: Ofir Bitton

accel/habanalabs/gaudi2: align embedded specs headers

2024-06-23T06:44:45Z

Align embedded headers to latest release. Reviewed-by: Tomer Tayar Signed-off-by: Ofir Bitton

accel/habanalabs/gaudi2: update interrupts related headers

2024-06-23T06:44:17Z

Align the interrupts related headers to latest release. Signed-off-by: Farah Kassabri Reviewed-by: Ofir Bitton Signed-off-by: Ofir Bitton

accel/habanalabs/gaudi2: move HMMU page tables to device memory

2024-02-26T07:30:40Z

Currently the HMMU page tables reside in the host memory, which will cause host access from the device for every page walk. This can affect PCIe bandwidth in certain scenarios. To prevent that problem, HMMU page tables will be moved to the device memory so the miss transaction will read the hops from there instead of going to the host. Signed-off-by: Farah Kassabri Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay

accel/habanalabs/gaudi2: use correct registers to dump QM CQ info

2023-12-19T09:09:43Z

The QM CQ PTR_LO/PTR_HI/TSIZE registers are for pushing a CQ entry, and although they are updated by HW even when descriptors are fetched by PQ and CB addresses are fed into CQ, the correct registers to use when dumping the CQ info are the ones with the _STS suffix. Signed-off-by: Tomer Tayar Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay

accel/habanalabs/gaudi2: get the correct QM CQ info upon an error

2023-12-19T09:09:43Z

Upon a QM error, the address/size from both the CQ and the ARC_CQ are printed, although the instruction that led to the error was received from only one of them. Moreover, in case of a QM undefined opcode, only one of these address/size sets will be captured based on the value of ARC_CQ_PTR. However, this value can be non-zero even if currently the CQ is used, in case the CQ/ARC_CQ are alternately used. Under the assumption of having a stop-on-error configuration, modify to use CP_STS.CUR_CQ field to get the relevant CQ for the QM error. Signed-off-by: Tomer Tayar Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay

accel/habanalabs: add support for Gaudi2C device

2023-12-19T09:09:43Z

Gaudi2 with PCI revision ID with the value of '3' represents Gaudi2C device and should be detected and initialized as Gaudi2. Signed-off-by: Oded Gabbay

accel/habanalabs/gaudi2: perform hard-reset upon PCIe AXI drain event

2023-10-09T09:37:24Z

Non-completed transactions from PCIe towards the device are handled by the AXI drain mechanism. This handling is in the PCIe level, but the transactions are still there in the device consuming some queues entries, and therefore the device must be reset. Modify to perform hard-reset upon PCIe AXI drain events. Signed-off-by: Tomer Tayar Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay