linux/drivers/acpi/cppc_acpi.c, branch v4.9

ACPI / CPPC: Support PCC with interrupt flag

2016-09-16T23:14:24Z

For PCC mailbox with interrupt flag, CPPC should call mbox_chan_txdone() function to notify the mailbox framework about TX completion. Signed-off-by: Hoan Tran Reviewed-by: Prashanth Prakash Signed-off-by: Rafael J. Wysocki

ACPI / CPPC: Add prefix cppc to cpudata structure name

2016-09-08T21:02:15Z

Since struct cpudata is defined in a header file, add prefix cppc_ to make it not a generic name. Otherwise it causes compile issue in locally define structure with the same name. Signed-off-by: Srinivas Pandruvada Signed-off-by: Rafael J. Wysocki

ACPI / CPPC: Add support for functional fixed hardware address

2016-09-08T21:02:14Z

The CPPC registers can also be accessed via functional fixed hardware addresse(FFH) in X86. Add support by modifying cpc_read and cpc_write to be able to read/write MSRs on x86 platform on per cpu basis. Also with this change, acpi_cppc_processor_probe doesn't bail out if address space id is not equal to PCC or memory address space and FFH is supported on the system. Signed-off-by: Srinivas Pandruvada Signed-off-by: Rafael J. Wysocki

ACPI / CPPC: check for error bit in PCC status field

2016-08-30T23:02:34Z

PCC status field exposes an error bit(2) to indicate any errors during the execution of last comamnd. This patch checks the error bit before notifying success/failure to the cpufreq driver. Signed-off-by: Prashanth Prakash Signed-off-by: Rafael J. Wysocki

ACPI / CPPC: move all PCC related information into pcc_data

2016-08-30T23:02:34Z

There are several global variables in cppc driver that are related to PCC channel used for CPPC. This patch collects all such information into a single consolidated structure(cppc_pcc_data). Signed-off-by: Prashanth Prakash Signed-off-by: Rafael J. Wysocki

ACPI / CPPC: add sysfs support to compute delivered performance

2016-08-30T23:02:34Z

The CPPC tables contain entries for per CPU feedback counters which allows us to compute the delivered performance over a given interval of time. The math for delivered performance per the CPPCv5.0+ spec is: reference perf * delta(delivered perf ctr)/delta(ref perf ctr) Maintaining deltas of the counters in the kernel is messy, as it depends on when the reads are triggered. (e.g. via the cpufreq ->get() interface). Also the ->get() interace only returns one value, so cant return raw values. So instead, leave it to userspace to keep track of raw values and do its math for CPUs it cares about. delivered and reference perf counters are exposed via the same sysfs file to avoid the potential "skid", if these values are read individually from userspace. Signed-off-by: Prashanth Prakash Signed-off-by: Ashwin Chaugule Signed-off-by: Rafael J. Wysocki

ACPI / CPPC: set a non-zero value for transition_latency

2016-08-30T23:02:33Z

Compute the expected transition latency for frequency transitions using the values from the PCCT tables when the desired perf register is in PCC. Signed-off-by: Prashanth Prakash Reviewed-by: Alexey Klimov Signed-off-by: Rafael J. Wysocki

ACPI / CPPC: support for batching CPPC requests

2016-08-30T23:02:33Z

CPPC defined in section 8.4.7 of ACPI 6.0 specification suggests "To amortize the cost of PCC transactions, OSPM should read or write all PCC registers via a single read or write command when possible" This patch enables opportunistic batching of frequency transition requests whenever the request happen to overlap in time. Currently the access to pcc is serialized by a spin lock which does not scale well as we increase the number of cores in the system. This patch improves the scalability by allowing the differnt CPU cores to update PCC subspace in parallel and by batching requests which will reduce the certain types of operation(checking command completion bit, ringing doorbell) by a significant margin. Profiling shows significant improvement in the overall effeciency to service freq. transition requests. With this patch we observe close to 30% of the frequency transition requests being batched with other requests while running apache bench on a ARM platform with 6 independent domains(or sets of related cpus). Signed-off-by: Prashanth Prakash Signed-off-by: Rafael J. Wysocki

ACPI / CPPC: acquire pcc_lock only while accessing PCC subspace

2016-08-30T23:02:33Z

We need to acquire pcc_lock only when we are accessing registers that are in the PCC subspsace. Signed-off-by: Prashanth Prakash Signed-off-by: Rafael J. Wysocki

ACPI / CPPC: restructure read/writes for efficient sys mapped reg ops

2016-08-30T23:02:33Z

For cases where sys mapped CPC registers need to be accessed frequently, it helps immensly to pre-map them rather than map and unmap for each operation. e.g. case where feedback counters are sys mem map registers. Restructure cpc_read/write and the cpc_regs structure to allow pre-mapping the system addresses and unmap them when the CPU exits. Signed-off-by: Ashwin Chaugule Signed-off-by: Prashanth Prakash Signed-off-by: Rafael J. Wysocki