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<title>linux/drivers/base/regmap/regcache-indexed.c, branch master</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=master</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2011-11-20T20:56:34Z</updated>
<entry>
<title>regmap: Remove indexed cache type</title>
<updated>2011-11-20T20:56:34Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@opensource.wolfsonmicro.com</email>
</author>
<published>2011-11-18T16:53:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4c691664583ef6a91f9ed0e08a75fbd30a5ffd5c'/>
<id>urn:sha1:4c691664583ef6a91f9ed0e08a75fbd30a5ffd5c</id>
<content type='text'>
There should be no situation where it offers any advantage over rbtree
and there are no current users so remove the code for simplicity.

Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
</entry>
<entry>
<title>regmap: Return a sensible error code if we fail to read the cache</title>
<updated>2011-10-10T09:24:03Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@opensource.wolfsonmicro.com</email>
</author>
<published>2011-10-09T12:23:31Z</published>
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<id>urn:sha1:6e6ace00a045251bd172b9b9c2379857bbff3dc7</id>
<content type='text'>
If a register isn't cached then let callers know that so they can fall
back or error handle appropriately.

Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
Acked-by: Dimitris Papastamos &lt;dp@opensource.wolfsonmicro.com&gt;
</content>
</entry>
<entry>
<title>regmap: Lock the sync path, ensure we use the lockless _regmap_write()</title>
<updated>2011-09-30T12:57:47Z</updated>
<author>
<name>Dimitris Papastamos</name>
<email>dp@opensource.wolfsonmicro.com</email>
</author>
<published>2011-09-29T13:36:25Z</published>
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<id>urn:sha1:13753a9088af23c61e2f5c10a8f3ea136d8ebab5</id>
<content type='text'>
Signed-off-by: Dimitris Papastamos &lt;dp@opensource.wolfsonmicro.com&gt;
Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
</entry>
<entry>
<title>regmap: Fix signed/unsigned comparison</title>
<updated>2011-09-27T12:27:09Z</updated>
<author>
<name>Dimitris Papastamos</name>
<email>dp@opensource.wolfsonmicro.com</email>
</author>
<published>2011-09-27T10:25:04Z</published>
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<id>urn:sha1:dfdc4448e078d06bdba0da52db7176437877788f</id>
<content type='text'>
Signed-off-by: Dimitris Papastamos &lt;dp@opensource.wolfsonmicro.com&gt;
Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
</entry>
<entry>
<title>regmap: Add the indexed cache support</title>
<updated>2011-09-19T18:06:32Z</updated>
<author>
<name>Dimitris Papastamos</name>
<email>dp@opensource.wolfsonmicro.com</email>
</author>
<published>2011-09-19T13:34:01Z</published>
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<id>urn:sha1:195af65ca92179ac2b524d35d732dc6fecec2744</id>
<content type='text'>
This is the simplest form of a cache available in regcache.  Any
registers whose default value is 0 are ignored.  If any of those
registers are modified in the future, they will be placed in the
cache on demand.  The cache layout is essentially using the provided
register defaults by the regcache core directly and does not re-map
it to another representation.

Signed-off-by: Dimitris Papastamos &lt;dp@opensource.wolfsonmicro.com&gt;
Signed-off-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
</content>
</entry>
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