<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/base/regmap/regcache.c, branch v3.18</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v3.18</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v3.18'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2014-09-29T19:49:42Z</updated>
<entry>
<title>Merge remote-tracking branch 'regmap/topic/cache' into regmap-next</title>
<updated>2014-09-29T19:49:42Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@kernel.org</email>
</author>
<published>2014-09-29T19:49:42Z</published>
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<id>urn:sha1:f5b313a2bcd4c436560c044c726d9ad84a3e4bb3</id>
<content type='text'>
</content>
</entry>
<entry>
<title>regmap: cache: Do not fail silently from regcache_sync calls</title>
<updated>2014-09-16T16:53:40Z</updated>
<author>
<name>Jarkko Nikula</name>
<email>jarkko.nikula@linux.intel.com</email>
</author>
<published>2014-09-16T11:04:14Z</published>
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<id>urn:sha1:f29a43206ae1adfadbb344f5ef9bc200784f9d61</id>
<content type='text'>
Call stack of regcache_sync calls may not emit any error message even if
operation was cancelled due an error in I/O driver. One such a silent error
is for instance if I2C bus driver doesn't receive ACK from the I2C device
and returns -EREMOTEIO.

Since many users of regcache_sync() don't check and print the error there is
no any indication that HW registers are potentially out of sync.

Signed-off-by: Jarkko Nikula &lt;jarkko.nikula@linux.intel.com&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>regmap: Don't attempt block writes when syncing cache on single_rw devices</title>
<updated>2014-08-31T12:22:37Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2014-08-27T12:09:12Z</published>
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<id>urn:sha1:5c1ebe7f73f9166893c3459915db8a09d6d1d715</id>
<content type='text'>
If the device can't support block writes then don't attempt to use raw
syncing which will automatically generate block writes for adjacent
registers, use the existing _single() block syncing implementation.

Reported-by: Jarkko Nikula &lt;jarkko.nikula@linux.intel.com&gt;
Tested-by: Jarkko Nikula &lt;jarkko.nikula@linux.intel.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>Merge remote-tracking branches 'regmap/topic/cache', 'regmap/topic/irq', 'regmap/topic/lock', 'regmap/topic/mmio', 'regmap/topic/nodev', 'regmap/topic/parse-val' and 'regmap/topic/patch' into regmap-next</title>
<updated>2014-03-28T11:50:43Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2014-03-28T11:50:43Z</published>
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<id>urn:sha1:6012b1f3424c4dc36369697845a9ca699887b0c7</id>
<content type='text'>
</content>
</entry>
<entry>
<title>regmap: cache: Don't attempt to sync non-writeable registers</title>
<updated>2014-03-19T10:38:56Z</updated>
<author>
<name>Dylan Reid</name>
<email>dgreid@chromium.org</email>
</author>
<published>2014-03-18T20:45:09Z</published>
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<id>urn:sha1:83f8475ce99fa1c44b03059b6cc5dcaae69b4819</id>
<content type='text'>
In the regcache_default_sync, if a register isn't writeable, then
_regmap_write will return an error and the rest of the sync will be
aborted.  Avoid this by checking if a register is writeable before
trying to sync it.

Signed-off-by: Dylan Reid &lt;dgreid@chromium.org&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
</entry>
<entry>
<title>regmap: cache: Step by stride in default sync</title>
<updated>2014-03-19T10:38:54Z</updated>
<author>
<name>Dylan Reid</name>
<email>dgreid@chromium.org</email>
</author>
<published>2014-03-18T20:45:08Z</published>
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<id>urn:sha1:756173285e87c792c6fa8eaaaf1217cfcf1416dd</id>
<content type='text'>
The default sync operation was still assuming a stride of one, fix it
to respect the reg_stride set in the map.

Signed-off-by: Dylan Reid &lt;dgreid@chromium.org&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
</entry>
<entry>
<title>regmap: Check stride of register patch as we register it</title>
<updated>2014-02-22T02:15:13Z</updated>
<author>
<name>Charles Keepax</name>
<email>ckeepax@opensource.wolfsonmicro.com</email>
</author>
<published>2014-02-21T19:37:10Z</published>
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<id>urn:sha1:7a7a70b49b51e90593ae072a9402d6615d05e895</id>
<content type='text'>
Currently, we check the registers in the patch are aligned to the
register stride everytime we sync the cache and the first time the patch
is written out is unchecked.

This patch checks the register patch when we first register it so the
first writes are no longer unchecked and then doesn't check on
subsequent syncs as the patch will be unchanged.

Signed-off-by: Charles Keepax &lt;ckeepax@opensource.wolfsonmicro.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
</entry>
<entry>
<title>regmap: cache: Handle stride &gt; 1 in sync_block_raw_flush</title>
<updated>2014-01-27T18:25:11Z</updated>
<author>
<name>Dylan Reid</name>
<email>dgreid@chromium.org</email>
</author>
<published>2014-01-24T23:40:39Z</published>
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<id>urn:sha1:78ba73eecd2256790926859849801c0446766c0a</id>
<content type='text'>
regcache_sync_block_raw_flush takes the address of the base register
and the address of one past the last register to write to.  "count" is
the number of registers in the range, not the number of bytes, it
should be (end addr - start addr) / stride. Without accounting for
strides greater than one, registers past the end might be synced or
the writeable_reg callback at the beginning of _regmap_raw_write will
fail and nothing will be written.

Signed-off-by: Dylan Reid &lt;dgreid@chromium.org&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
</entry>
<entry>
<title>regmap: Use async I/O during cache sync</title>
<updated>2013-10-10T20:15:23Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2013-10-10T20:06:32Z</published>
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<id>urn:sha1:affbe886e712437c25b575eac5fde5886bb42aec</id>
<content type='text'>
Try to speed up I/O a little by not synchronising until we are finished
scheduling writes. A brief survey of existing users suggests we have none
that would currently benefit from an async cache sync.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
</entry>
<entry>
<title>regmap: Simplify the initiation of async I/O</title>
<updated>2013-10-09T13:05:24Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2013-10-09T11:28:52Z</published>
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<id>urn:sha1:0a8198094da895c8d5db95812fe9de7027d808e4</id>
<content type='text'>
Rather than passing a flag around through the entire call stack store it
in the regmap struct and read it when required. This minimises the
visibility of the feature through the API, minimising the code updates
needed to use it more widely.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
</entry>
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