linux/drivers/bus/Makefile, branch master

Merge tag 'devicetree-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

2026-04-17T21:09:02Z

Pull devicetree updates from Rob Herring: "DT core: - Cleanup of the reserved memory code to keep CMA specifics in CMA code - Add and convert several users to new of_machine_get_match() helper - Validate nul termination in string properties - Update dtc to upstream v1.7.2-69-g53373d135579 - Limit matching reserved memory devices to /reserved-memory nodes - Fix some UAF in unittests - Remove Baikal SoC bus driver - Fix false DT_SPLIT_BINDING_PATCH checkpatch warning - Allow fw_devlink device-tree on x86 - Fix kerneldoc return description for of_property_count_elems_of_size() DT bindings: - Add fsl,imx25-aips, fsl,imx25-tcq, qcom,eliza-pdc, qcom,eliza-spmi-pmic-arb, qcom,hawi-imem, qcom,milos-imem, qcom,hawi-pdc, and lg,sw49410 bindings - Convert arm,vexpress-scc to DT schema - Deprecate Qualcomm generic CPU compatibles. Add Apple M3 CPU cores. - Move some dual-link display panels to the dual-link schema - Drop mux controller node name constraints - Remove Baikal SoC bus bindings - Fix a false warning in the thermal trip node binding" * tag 'devicetree-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (39 commits) dt-bindings: display: panel: panel-simple: Add lg,sw49410 compatible dt-bindings: display: ti, am65x-dss: Fix AM62L DSS reg and clock constraints dt-bindings: display: simple: Move Innolux G156HCE-L01 panel to dual-link dt-bindings: display: simple: Move AUO 21.5" FHD to dual-link dt-bindings: thermal: Fix false warning with 'phandle' in trips nodes of: unittest: fix use-after-free in testdrv_probe() of: unittest: fix use-after-free in of_unittest_changeset() dt-bindings: qcom,pdc: document the Hawi Power Domain Controller dt-bindings: ARM: arm,vexpress-scc: convert to DT schema drivers/of: fdt: validate flat DT string properties before string use drivers/of: fdt: validate stdout-path properties before parsing them dt-bindings: sram: Document qcom,hawi-imem compatible dt-bindings: sram: Allow multiple-word prefixes to sram subnode dt-bindings: sram: Document qcom,milos-imem scripts/dtc: Update to upstream version v1.7.2-69-g53373d135579 of: property: Allow fw_devlink device-tree on x86 dt-bindings: arm: cpus: Add Apple M3 CPU core compatibles dt-bindings: display: lt8912b: Drop redundant endpoint properties dt-bindings: opp-v2: Fix example 3 CPU reg value dt-bindings: connector: add pd-disable dependency ...

drivers: bus: add the stm32 debug bus driver

2026-03-25T16:40:22Z

Add the stm32 debug bus driver that is responsible of checking the debug subsystem accessibility before probing the related peripheral drivers. This driver is OP-TEE dependent and relies on the STM32 debug access PTA. Signed-off-by: Gatien Chevallier Link: https://lore.kernel.org/r/20260226-debug_bus-v6-6-5d794697798d@foss.st.com Signed-off-by: Alexandre Torgue

bus: Remove not-going-to-be-supported code for Baikal SoC

2026-03-11T22:43:43Z

As noticed in the discussion [1] the Baikal SoC and platforms are not going to be finalized, hence remove stale code. Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1] Signed-off-by: Andy Shevchenko Reviewed-by: Randy Dunlap Link: https://patch.msgid.link/20260227072726.1142944-2-andriy.shevchenko@linux.intel.com Signed-off-by: Rob Herring (Arm)

bus: add driver for IMX AIPSTZ bridge

2025-07-01T14:23:21Z

The secure AHB to IP Slave (AIPSTZ) bus bridge provides access control configurations meant to restrict access to certain peripherals. Some of the configurations include: 1) Marking masters as trusted for R/W. Based on this (and the configuration of the accessed peripheral), the bridge may choose to abort the R/W transactions issued by certain masters. 2) Allowing/disallowing write accesses to peripherals. Add driver for this IP. Since there's currently no framework for access controllers (and since there's currently no need for having flexibility w.r.t the configurations) all this driver does is it applies a relaxed, "default" configuration, in which all masters are trusted for R/W. Note that some instances of this IP (e.g: AIPSTZ5 on i.MX8MP) may be tied to a power domain and may lose their configuration when the domain is powered off. This is why the configuration has to be restored when the domain is powered on. Co-developed-by: Daniel Baluta Signed-off-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea Signed-off-by: Shawn Guo

bus: etzpc: introduce ETZPC firewall controller driver

2024-04-25T12:44:39Z

ETZPC is a peripheral and memory firewall controller that filter accesses based on Arm TrustZone secure state and Arm CPU privilege execution level. It handles MCU isolation as well. Signed-off-by: Gatien Chevallier Signed-off-by: Alexandre Torgue

bus: rifsc: introduce RIFSC firewall controller driver

2024-04-24T12:30:35Z

RIFSC is a peripheral firewall controller that filter accesses based on Arm TrustZone secure state, Arm CPU privilege execution level and Compartment IDentification of the STM32 SoC subsystems. Signed-off-by: Gatien Chevallier Signed-off-by: Alexandre Torgue

firewall: introduce stm32_firewall framework

2024-04-05T14:49:14Z

Introduce a STM32 firewall framework that offers to firewall consumers different firewall services such as the ability to check their access rights against their firewall controller(s). The STM32 firewall framework offers a generic API for STM32 firewall controllers that is defined in their drivers to best fit the specificity of each firewall. There are various types of firewalls: -Peripheral firewalls that filter accesses to peripherals -Memory firewalls that filter accesses to memories or memory regions -No type for undefined type of firewall Signed-off-by: Gatien Chevallier Signed-off-by: Alexandre Torgue

bus: add driver for initializing the SSC bus on (some) qcom SoCs

2022-04-19T18:03:57Z

Add bindings for the AHB bus which exposes the SSC (Snapdragon Sensor Core) block in the global address space. This bus (and the SSC block itself) is present on certain qcom SoCs. In typical configuration, this bus (as some of the clocks and registers that we need to manipulate) is not accessible to Linux, and the resources on this bus are indirectly accessed by communicating with a hexagon CPU core residing in the SSC block. In this configuration, the hypervisor is the one performing the bus initialization for the purposes of bringing the hexagon CPU core out of reset. However, it is possible to change the configuration, in which case this driver will initialize the bus. In combination with drivers for resources on the SSC bus, this driver can aid in debugging, and for example with a TLMM driver can be used to directly access SSC-dedicated GPIO pins, removing the need to commit to a particular usecase during hw design. Finally, until open firmware for the hexagon core is available, this approach allows for using sensors hooked up to SSC-dedicated GPIO pins on mainline Linux simply by utilizing the existing in-tree drivers for these sensors. Signed-off-by: Michael Srba Reviewed-by: Jeffrey Hugo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411072156.24451-5-michael.srba@seznam.cz

bus: mhi: Move host MHI code to "host" directory

2022-03-18T13:02:54Z

In preparation of the endpoint MHI support, let's move the host MHI code to its own "host" directory and adjust the toplevel MHI Kconfig & Makefile. While at it, let's also move the "pci_generic" driver to "host" directory as it is a host MHI controller driver. Reviewed-by: Hemant Kumar Reviewed-by: Alex Elder Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20220301160308.107452-5-manivannan.sadhasivam@linaro.org Signed-off-by: Greg Kroah-Hartman

drivers: bus: Delete CONFIG_SIMPLE_PM_BUS

2021-10-05T15:47:22Z

The simple-pm-bus driver is mandatory for CONFIG_OF based platforms to work with fw_devlink. So, always compile it in for CONFIG_OF and delete the config since it's no longer necessary. Tested-by: Ulf Hansson Tested-by: Geert Uytterhoeven Tested-by: Damien Le Moal Cc: Rob Herring Signed-off-by: Saravana Kannan Link: https://lore.kernel.org/r/20210929000735.585237-3-saravanak@google.com Signed-off-by: Greg Kroah-Hartman