linux/drivers/clk/meson, branch master

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-22T01:09:51Z

This was done entirely with mindless brute force, using git grep -l '\

treewide: Replace kmalloc with kmalloc_obj for non-scalar types

2026-02-21T09:02:28Z

This is the result of running the Coccinelle script from scripts/coccinelle/api/kmalloc_objs.cocci. The script is designed to avoid scalar types (which need careful case-by-case checking), and instead replace kmalloc-family calls that allocate struct or union object instances: Single allocations: kmalloc(sizeof(TYPE), ...) are replaced with: kmalloc_obj(TYPE, ...) Array allocations: kmalloc_array(COUNT, sizeof(TYPE), ...) are replaced with: kmalloc_objs(TYPE, COUNT, ...) Flex array allocations: kmalloc(struct_size(PTR, FAM, COUNT), ...) are replaced with: kmalloc_flex(*PTR, FAM, COUNT, ...) (where TYPE may also be *VAR) The resulting allocations no longer return "void *", instead returning "TYPE *". Signed-off-by: Kees Cook

clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro

2026-01-06T08:52:21Z

There's no need to calculate HHI_HDMI_PLL_CNTL + 8 when we have a HHI_HDMI_PLL_CNTL3 macro that has the correct offset already. No functional changes, this makes it easier to compare the driver with the datasheets. Signed-off-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20260105204710.447779-4-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet

clk: meson: g12a: Limit the HDMI PLL OD to /4

2026-01-06T08:52:21Z

GXBB has the HDMI PLL OD in the HHI_HDMI_PLL_CNTL2 register while for G12A/G12B/SM1 the OD has moved to HHI_HDMI_PLL_CNTL0. At first glance the rest of the OD setup seems identical. However, looking at the downstream kernel sources as well as testing shows that G12A/G12B/SM1 only supports three OD values: - register value 0 means: divide by 1 - register value 1 means: divide by 2 - register value 2 means: divide by 4 Downstream sources are also only using OD register values 0, 1 and 2 for G12A/G12B/SM1 (while for GXBB the downstream kernel sources are also using value 3 which means: divide by 8). Add clk_div_table and have it replace the CLK_DIVIDER_POWER_OF_TWO flag to make the kernel's view of this register match with how the hardware actually works. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20260105204710.447779-3-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet

clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs

2026-01-06T08:51:48Z

GXBB has the HDMI PLL OD in the HHI_HDMI_PLL_CNTL2 register while for GXL/GXM the OD has moved to HHI_HDMI_PLL_CNTL3. At first glance the rest of the OD setup seems identical. However, looking at the downstream kernel sources as well as testing shows that GXL only supports three OD values: - register value 0 means: divide by 1 - register value 1 means: divide by 2 - register value 2 means: divide by 4 Using register value 3 (which on GXBB means: divide by 8) still divides by 4 as verified using meson-clk-measure. Downstream sources are also only using OD register values 0, 1 and 2 for GXL (while for GXBB the downstream kernel sources are also using value 3). Add clk_div_table and have it replace the CLK_DIVIDER_POWER_OF_TWO flag to make the kernel's view of this register match with how the hardware actually works. Fixes: 69d92293274b ("clk: meson: add the gxl hdmi pll") Signed-off-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20260105204710.447779-2-martin.blumenstingl@googlemail.com Signed-off-by: Jerome Brunet

clk: amlogic: remove potentially unsafe flags from S4 video clocks

2025-12-15T09:56:08Z

The video clocks enci, encp, vdac and hdmitx share the same clock source. Adding CLK_SET_RATE_PARENT to the mux may unintentionally change the shared parent clock, which could affect other video clocks. Signed-off-by: Chuan Liu Link: https://lore.kernel.org/r/20250919-add_video_clk-v6-3-fe223161fb3f@amlogic.com Signed-off-by: Jerome Brunet

clk: amlogic: add video-related clocks for S4 SoC

2025-12-15T09:56:08Z

Add video encoder, demodulator and CVBS clocks. Signed-off-by: Chuan Liu Link: https://lore.kernel.org/r/20250919-add_video_clk-v6-2-fe223161fb3f@amlogic.com Signed-off-by: Jerome Brunet

clk: meson: t7: add t7 clock peripherals controller driver

2025-12-15T09:42:29Z

Add Peripheral clock controller driver for the Amlogic T7 SoC family. Signed-off-by: Jian Hu Link: https://lore.kernel.org/r/20251212022619.3072132-6-jian.hu@amlogic.com Signed-off-by: Jerome Brunet

clk: meson: t7: add support for the T7 SoC PLL clock

2025-12-15T09:42:29Z

Add PLL clock controller driver for the Amlogic T7 SoC family. Signed-off-by: Jian Hu Link: https://lore.kernel.org/r/20251212022619.3072132-5-jian.hu@amlogic.com Signed-off-by: Jerome Brunet

clk: amlogic: fix recent code refactoring

2025-09-20T04:58:50Z

Commit 4c4e17f27013 ("clk: amlogic: naming consistency alignment") refactored some internals in the g12a meson clock driver. Unfortunately it introduced a bug in the clock init data, which results in the following kernel panic: Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 Mem abort info: ... Data abort info: ... [0000000000000000] user address but active_mm is swapper Internal error: Oops: 0000000096000004 [#1] SMP Modules linked in: CPU: 4 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.17.0-rc1+ #11158 PREEMPT Hardware name: Hardkernel ODROID-N2 (DT) pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : __clk_register+0x60/0x92c lr : __clk_register+0x48/0x92c ... Call trace: __clk_register+0x60/0x92c (P) devm_clk_hw_register+0x5c/0xd8 meson_eeclkc_probe+0x74/0x110 g12a_clkc_probe+0x2c/0x58 platform_probe+0x5c/0xac really_probe+0xbc/0x298 __driver_probe_device+0x78/0x12c driver_probe_device+0xdc/0x164 __driver_attach+0x9c/0x1ac bus_for_each_dev+0x74/0xd0 driver_attach+0x24/0x30 bus_add_driver+0xe4/0x208 driver_register+0x60/0x128 __platform_driver_register+0x24/0x30 g12a_clkc_driver_init+0x1c/0x28 do_one_initcall+0x64/0x308 kernel_init_freeable+0x27c/0x4f8 kernel_init+0x20/0x1d8 ret_from_fork+0x10/0x20 Code: 52800038 aa0003fc b9010018 52819801 (f9400260) ---[ end trace 0000000000000000 ]--- Fix this by correcting the clock init data. Fixes: 4c4e17f27013 ("clk: amlogic: naming consistency alignment") Signed-off-by: Marek Szyprowski Tested-by: Neil Armstrong # on BananPi M2S Reviewed-by: Neil Armstrong Reviewed-by: Jerome Brunet Signed-off-by: Stephen Boyd