linux/drivers/clk/qcom, branch v4.6

clk: qcom: ipq4019: add some fixed clocks for ddrppl and fepll

2016-03-29T23:31:16Z

Drivers for these don't exist yet so we will add them as fixed clocks so we don't BUG() if we change clocks that reference these clocks. Signed-off-by: Matthew McClintock Signed-off-by: Stephen Boyd

clk: qcom: ipq4019: switch remaining defines to enums

2016-03-29T23:31:11Z

When this was added not all the remaining defines were switched over to use enums, so let's complete that process here Reported-by: Stephen Boyd Signed-off-by: Matthew McClintock Signed-off-by: Stephen Boyd

clk: qcom: Make reset_control_ops const

2016-03-29T23:30:26Z

The qcom_reset_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel Signed-off-by: Stephen Boyd

clk: qcom: Remove CLK_IS_ROOT

2016-03-04T20:53:53Z

This flag is a no-op now. Remove usage of the flag. Signed-off-by: Stephen Boyd

clk: qcom: msm8960: Fix ce3_src register offset

2016-03-02T22:31:31Z

The offset seems to have been copied from the sata clk. Fix it so that enabling the crypto engine source clk works. Tested-by: Srinivas Kandagatla Tested-by: Bjorn Andersson Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd

clk: qcom: Fix pre-divider usage for pixel RCG

2016-02-29T20:57:06Z

The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading its current value from the NS register. Using the pre-divider wasn't really intended when creating these ops. The pixel RCG was only intended to achieve fractional multiplication provided in the pixel_table array. Leaving the pre-divider to the existing register value results in a wrong pixel clock when the bootloader sets up the display. This was left unidentified because the IFC6410 Plus board on which this was verified didn't have a bootloader that configured the display. Don't set the RCG pre-divider in freq_tbl to the existing NS register value. Force it to 1 and only use the M/N counter to achieve the desired fractional multiplication. Cc: Vinay Simha Signed-off-by: Archit Taneja Tested-by: John Stultz Signed-off-by: Stephen Boyd

Merge branch 'clk-ipq4019' into clk-next

2016-02-25T22:32:27Z

* clk-ipq4019: clk: qcom: Add IPQ4019 Global Clock Controller support

clk: qcom: Add IPQ4019 Global Clock Controller support

2016-02-25T22:32:12Z

This patch adds support for the global clock controller found on the IPQ4019 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Pradeep Banavathi Signed-off-by: Senthilkumar N L Signed-off-by: Varadarajan Narayanan Signed-off-by: Matthew McClintock Acked-by: Andy Gross [sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb] Signed-off-by: Stephen Boyd

clk: qcom: msm8960: fix ce3_core clk enable register

2016-02-22T22:15:53Z

This patch corrects the enable register offset which is actually 0x36cc instead of 0x36c4 Signed-off-by: Srinivas Kandagatla Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd

Merge branch 'clk-fixes' into clk-next

2016-02-19T03:17:29Z

* clk-fixes: clk: gpio: Really allow an optional clock= DT property Revert "clk: qcom: Specify LE device endianness"