linux/drivers/clk, branch v3.12

clk: fixup argument order when setting VCO parameters

2013-10-08T06:01:07Z

The order of arguments in the call to vco_set() for the ICST clocks appears to have been switched in error, which results in the VCO not being initialised correctly. This in turn stops the integrated LCD on things like Integrator/CP from working correctly. This patch fixes the order and restores the expected functionality. Reviewed-by: Linus Walleij Signed-off-by: Jonathan Austin Signed-off-by: Mike Turquette Cc: stable@vger.kernel.org

clk: socfpga: Fix incorrect sdmmc clock name

2013-10-08T01:37:49Z

The SD/MMC clock is named "sdmmc_clk", and NOT "mmc_clk". Because of this, the SD driver was getting the incorrect clock value. This prevented the SD driver from initializing correctly. Signed-off-by: Dinh Nguyen CC: Arnd Bergmann CC: Olof Johansson Reviewed-by: Pavel Machek Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette

clk: armada-370: fix tclk frequencies

2013-10-07T00:39:46Z

This patch fixes the tclk frequency array for the Armada-370 SoC. This bug has been introduced by commit 6b72333d ("clk: mvebu: add Armada 370 SoC-centric clock init"). A wrong tclk frequency affects the following drivers: mvsdio, mvneta, i2c-mv64xxx and mvebu-devbus. This list may be incomplete. About the mvneta Ethernet driver, note that the tclk frequency is used to compute the Rx time coalescence. Then, this bug harms the coalescence configuration and also degrades the networking performances with the default values. Signed-off-by: Simon Guinot Cc: Andrew Lunn Cc: Gregory CLEMENT Cc: Sebastian Hesselbarth Acked-by: Jason Cooper Cc: stable@vger.kernel.org Signed-off-by: Michael Turquette

clk: nomadik: set all timers to use 2.4 MHz TIMCLK

2013-10-02T04:39:56Z

This fixes a regression for the Nomadik on the main system timers. The Nomadik seemed a bit slow and its heartbeat wasn't looking healthy. And it was not strange, because it has been connected to the 32768 Hz clock at boot, while being told by the clock driver that it was 2.4MHz. Actually connect the TIMCLK to 2.4MHz by default as this is what we want for nice scheduling, clocksource and clock event. Cc: stable@vger.kernel.org Signed-off-by: Linus Walleij Signed-off-by: Mike Turquette

Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux

2013-09-09T22:49:04Z

Pull clock framework changes from Michael Turquette: "The common clk framework changes for 3.12 are dominated by clock driver patches, both new drivers and fixes to existing. A high percentage of these are for Samsung platforms like Exynos. Core framework fixes and some new features like automagical clock re-parenting round out the patches" * tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits) clk: only call get_parent if there is one clk: samsung: exynos5250: Simplify registration of PLL rate tables clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 clk: samsung: exynos4: Register PLL rate tables for Exynos4210 clk: samsung: exynos4: Reorder registration of mout_vpllsrc clk: samsung: pll: Add support for rate configuration of PLL46xx clk: samsung: pll: Use new registration method for PLL46xx clk: samsung: pll: Add support for rate configuration of PLL45xx clk: samsung: pll: Use new registration method for PLL45xx clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls clk: samsung: exynos4: Remove checks for DT node clk: samsung: exynos4: Remove unused static clkdev aliases clk: samsung: Modify _get_rate() helper to use __clk_lookup() clk: samsung: exynos4: Use separate aliases for cpufreq related clocks clocksource: samsung_pwm_timer: Get clock from device tree ARM: dts: exynos4: Specify PWM clocks in PWM node pwm: samsung: Update DT bindings documentation to cover clocks clk: Move symbol export to proper location clk: fix new_parent dereference before null check clk: wm831x: Initialise wm831x pointer on init ...

clk: only call get_parent if there is one

2013-09-09T21:10:10Z

In __clk_init(), after a clock is mostly initialized, a scan is done of the orphan clocks to see if the clock being registered is the parent of any of them. This code assumes that any clock that provides a get_parent method actually has at least one parent, and that's not a valid assumption. As a result, an orphan clock with no parent can return *something* as the parent index, and that value is blindly used to dereference the orphan's parent_names[] array (which will be ZERO_SIZE_PTR or NULL). Fix this by ensuring get_parent is only called for orphans with at least one parent. Signed-off-by: Alex Elder Signed-off-by: Mike Turquette

clk: samsung: exynos5250: Simplify registration of PLL rate tables

2013-09-06T20:34:05Z

Since the _get_rate() helper has been modified to use __clk_lookup() internally, checking of PLL input rates can be done using it and so the registration code can be simplified. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Reviewed-by: Sylwester Nawrocki Signed-off-by: Mike Turquette

clk: samsung: exynos4: Register PLL rate tables for Exynos4x12

2013-09-06T20:34:01Z

This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4x12 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Reviewed-by: Sylwester Nawrocki Signed-off-by: Mike Turquette

clk: samsung: exynos4: Register PLL rate tables for Exynos4210

2013-09-06T20:33:57Z

This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4210 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Reviewed-by: Sylwester Nawrocki Signed-off-by: Mike Turquette

clk: samsung: exynos4: Reorder registration of mout_vpllsrc

2013-09-06T20:33:52Z

Since PLL input frequency must be known before PLL registration, mout_vpllsrc clock which is a reference clock of VPLL must be registered before VPLL. This patch reorders clock registration to register mout_vpllsrc before VPLL. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Reviewed-by: Sylwester Nawrocki Signed-off-by: Mike Turquette