linux/drivers/clk, branch v3.19

clk: fix possible null pointer dereference

2015-01-17T19:33:57Z

The commit 646cafc6 (clk: Change clk_ops->determine_rate to return a clk_hw as the best parent) opens a possibility for null pointer dereference, fix this. Signed-off-by: Stanimir Varbanov Reviewed-by: Stephen Boyd Signed-off-by: Michael Turquette

Revert "clk: ppc-corenet: Fix Section mismatch warning"

2015-01-17T19:27:16Z

This reverts commit da788acb28386aa896224e784954bb73c99ff26c. That commit tried to fix the section mismatch warning by moving the ppc_corenet_clk_driver struct to init section. This is definitely wrong because the kernel would free the memories occupied by this struct after boot while this driver is still registered in the driver core. The kernel would panic when accessing this driver struct. Cc: stable@vger.kernel.org # 3.17 Signed-off-by: Kevin Hao Acked-by: Scott Wood Signed-off-by: Michael Turquette

clk: rockchip: fix deadlock possibility in cpuclk

2015-01-17T19:22:39Z

Lockdep reported a possible deadlock between the cpuclk lock and for example the i2c driver. CPU0 CPU1 ---- ---- lock(clk_lock); local_irq_disable(); lock(&(&i2c->lock)->rlock); lock(clk_lock); lock(&(&i2c->lock)->rlock); *** DEADLOCK *** The generic clock-types of the core ccf already use spin_lock_irqsave when touching clock registers, so do the same for the cpuclk. Signed-off-by: Heiko Stuebner Reviewed-by: Doug Anderson Signed-off-by: Michael Turquette [mturquette@linaro.org: removed initialization of "flags"]

clk: berlin: bg2q: remove non-exist "smemc" gate clock

2015-01-13T18:58:43Z

The "smemc" clock is removed on BG2Q SoCs. In fact, bit19 of clkenable register is for nfc. Current code use bit19 for non-exist "smemc" incorrectly, this prevents eMMC from working due to the sdhci's "core" clk is still gated. Signed-off-by: Jisheng Zhang Cc: stable@vger.kernel.org # 3.16+ Signed-off-by: Michael Turquette

clk: at91: keep slow clk enabled to prevent system hang

2015-01-13T18:54:01Z

All slow clk users are not properly claiming it (get + prepare + enable) before using it. If all users properly claiming this clock release it, the clock is disabled, but faulty users still depends on it, and the system hangs. This fix prevents the slow clock from being disabled, and should solve the hanging issue, but offending drivers should be patched to properly claim this clock. Signed-off-by: Boris Brezillon Reported-by: Bo Shen Cc: stable@vger.kernel.org Signed-off-by: Michael Turquette

clk: rockchip: fix rk3288 cpuclk core dividers

2014-12-28T22:31:44Z

Commit 0e5bdb3f9fa5 (clk: rockchip: switch to using the new cpuclk type for armclk) didn't take into account that the divider used on rk3288 are of the (n+1) type. The rk3066 and rk3188 socs use more complex divider types making it necessary for the list-elements to be the real register-values to write. Therefore reduce divider values in the table accordingly so that they really are the values that should be written to the registers and match the dividers actually specified for the rk3288. Reported-by: Sonny Rao Fixes: 0e5bdb3f9fa5 ("clk: rockchip: switch to using the new cpuclk type for armclk") Signed-off-by: Heiko Stuebner Reviewed-by: Doug Anderson Cc: stable@vger.kernel.org

clk: rockchip: fix rk3066 pll lock bit location

2014-12-28T22:30:08Z

The bit locations indicating the locking status of the plls on rk3066 are shifted by one to the right when compared to the rk3188, bits [7:4] instead of [8:5] on the rk3188, thus indicating the locking state of the wrong pll or a completely different information in case of the gpll. The recently introduced pll init code exposed that problem on some rk3066 boards when it tried to bring the boot-pll value in line with the value from the rate table. Fix this by defining separate pll definitions for rk3066 with the correct locking indices. Signed-off-by: Heiko Stuebner Fixes: 2c14736c75db ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks") Tested-by: FUKAUMI Naoki Cc: stable@vger.kernel.org

clk: rockchip: Fix clock gate for rk3188 hclk_emem_peri

2014-12-21T14:21:28Z

Do not disable clock gate "hclk_emem_peri", otherwise EMAC clocks no longer work and it breaks ethernet on RK3066 and RK3188. It fixes a regression introduced by commit 78eaf6095cc7 ("clk: rockchip: disable unused clocks"). Signed-off-by: Romain Perier Fixes: 78eaf6095cc7 ("clk: rockchip: disable unused clocks") Signed-off-by: Heiko Stuebner

clk: rockchip: add CLK_IGNORE_UNUSED flag to fix rk3066/rk3188 USB Host

2014-12-21T14:18:24Z

This patch adds CLK_IGNORE_UNUSED flag to hclk_usb_peri, hclk_usbotg0 and hclk_usbotg1 because these clocks must remain enabled to use the USB controllers in host mode. This fixes a regression introduced by commit 78eaf6095cc7 ("clk: rockchip: disable unused clocks"). Signed-off-by: Julien CHAUVEAU Fixes: 78eaf6095cc7 ("clk: rockchip: disable unused clocks") Reviewed-by: Romain Perier Tested-by: Romain Perier Signed-off-by: Heiko Stuebner

Merge tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux

2014-12-21T00:42:36Z

Pull clk framework updates from Mike Turquette: "This is much later than usual due to several last minute bugs that had to be addressed. As usual the majority of changes are new drivers and modifications to existing drivers. The core recieved many fixes along with the groundwork for several large changes coming in the future which will better parition clock providers from clock consumers" * tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated ARM: OMAP3: clock: fix boot breakage in legacy mode ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs clk: Really fix deadlock with mmap_sem clk: mmp: fix sparse non static symbol warning clk: Change clk_ops->determine_rate to return a clk_hw as the best parent clk: change clk_debugfs_add_file to take a struct clk_hw clk: Don't expose __clk_get_accuracy clk: Don't try to use a struct clk* after it could have been freed clk: Remove unused function __clk_get_prepare_count clk: samsung: Fix double add of syscore ops after driver rebind clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi clk: samsung: exynos4415: Fix build with PM_SLEEP disabled clk: samsung: remove unnecessary inclusion of header files from clk.h clk: samsung: remove unnecessary CONFIG_OF from clk.c clk: samsung: Spelling s/bwtween/between/ clk: rockchip: Add support for the mmc clock phases using the framework clk: rockchip: add bindings for the mmc clocks clk: rockchip: rk3288 export i2s0_clkout for use in DT clk: rockchip: use clock ID for DMC (memory controller) on rk3288 ...