linux/drivers/clk, branch v6.17

Merge tag 'sunxi-clk-fixes-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes

2025-09-20T04:28:01Z

Pull an Allwinner clk driver fix from Chen-Yu Tsai: - One fix for the clock rate readback on the recently added dual divider clocks * tag 'sunxi-clk-fixes-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: mp: Fix dual-divider clock rate readback

clk: sunxi-ng: mp: Fix dual-divider clock rate readback

2025-09-10T15:45:48Z

When dual-divider clock support was introduced, the P divider offset was left out of the .recalc_rate readback function. This causes the clock rate to become bogus or even zero (possibly due to the P divider being 1, leading to a divide-by-zero). Fix this by incorporating the P divider offset into the calculation. Fixes: 45717804b75e ("clk: sunxi-ng: mp: introduce dual-divider clock") Reviewed-by: Andre Przywara Link: https://patch.msgid.link/20250830170901.1996227-4-wens@kernel.org Signed-off-by: Chen-Yu Tsai

clk: renesas: mstp: Add genpd OF provider at postcore_initcall()

2025-08-18T07:36:55Z

Genpd OF providers must now be registered after genpd bus registration. However, cpg_mstp_add_clk_domain() is only called from CLK_OF_DECLARE(), which is too early. Hence on R-Car M1A, R-Car H1, and RZ/A1, the CPG/MSTP Clock Domain fails to register, and any devices residing in that clock domain fail to probe. Fix this by splitting initialization into two steps: - The first part keeps on registering the PM domain with genpd at CLK_OF_DECLARE(), - The second and new part moves the registration of the genpd OF provider to a postcore_initcall(). See also commit c5ae5a0c61120d0c ("pmdomain: renesas: rcar-sysc: Add genpd OF provider at postcore_initcall"). Fixes: 18a3a510ecfd0e50 ("pmdomain: core: Add the genpd->dev to the genpd provider bus") Signed-off-by: Geert Uytterhoeven Reviewed-by: Ulf Hansson Link: https://lore.kernel.org/81ef5f8d5d31374b7852b05453c52d2f735062a2.1755073087.git.geert+renesas@glider.be

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2025-07-31T20:36:27Z

Pull clk updates from Stephen Boyd: "This is the usual collection of primarily clk driver updates. The big part of the diff is all the new Qualcomm clk drivers added for a few SoCs they're working on. The other two vendors with significant work this cycle are Renesas and Amlogic. Renesas adds a bunch of clks to existing drivers and supports some new SoCs while Amlogic is starting a significant refactoring to simplify their code. The core framework gained a pair of helpers to get the 'struct device' or 'struct device_node' associated with a 'struct clk_hw'. Some associated KUnit tests were added for these simple helpers as well. Beyond that core change there are lots of little fixes throughout the clk drivers for the stuff we see every day, wrong clk driver data that affects tree topology or supported frequencies, etc. They're not found until the clks are actually used by some consumer device driver. New Drivers: - Global, display, gpu, video, camera, tcsr, and rpmh clock controller for the Qualcomm Milos SoC - Camera, display, GPU, and video clock controllers for Qualcomm QCS615 - Video clock controller driver for Qualcomm SM6350 - Camera clock controller driver for Qualcomm SC8180X - I3C clocks and resets on Renesas RZ/G3E - Expanded Serial Peripheral Interface (xSPI) clocks and resets on Renesas RZ/V2H(P) and RZ/V2N - SPI (RSPI) clocks and resets on Renesas RZ/V2H(P) - SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H - Ethernet clocks and resets on Renesas RZ/G3E - Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs - Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N - Timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on Renesas RZ/V2N Updates: - Support atomic PWMs in the PWM clk driver - clk_hw_get_dev() and clk_hw_get_of_node() helpers - Replace round_rate() with determine_rate() in various clk drivers - Convert clk DT bindings to DT schema format for DT validation - Various clk driver cleanups and refactorings from static analysis tools and possibly real humans - A lot of little fixes here and there to things like clk tree topology, missing frequencies, flagging clks as critical, etc" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (216 commits) clk: clocking-wizard: Fix the round rate handling for versal clk: Fix typos clk: spacemit: ccu_pll: fix error return value in recalc_rate callback clk: tegra: periph: Make tegra_clk_periph_ops static clk: tegra: periph: Fix error handling and resolve unsigned compare warning clk: imx: scu: convert from round_rate() to determine_rate() clk: imx: pllv4: convert from round_rate() to determine_rate() clk: imx: pllv3: convert from round_rate() to determine_rate() clk: imx: pllv2: convert from round_rate() to determine_rate() clk: imx: pll14xx: convert from round_rate() to determine_rate() clk: imx: pfd: convert from round_rate() to determine_rate() clk: imx: frac-pll: convert from round_rate() to determine_rate() clk: imx: fracn-gppll: convert from round_rate() to determine_rate() clk: imx: fixup-div: convert from round_rate() to determine_rate() clk: imx: cpu: convert from round_rate() to determine_rate() clk: imx: busy: convert from round_rate() to determine_rate() clk: imx: composite-93: remove round_rate() in favor of determine_rate() clk: imx: composite-8m: remove round_rate() in favor of determine_rate() clk: qcom: Remove redundant pm_runtime_mark_last_busy() calls clk: imx: Remove redundant pm_runtime_mark_last_busy() calls ...

Merge branch 'clk-fixes' into clk-next

2025-07-31T16:10:06Z

Resolve conflicts with i.MX95 changes 88768d6f8c13 ("clk: imx95-blk-ctl: Rename lvds and displaymix csr blk") in clk-imx and aacc875a448d ("clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data") in clk-fixes. * clk-fixes: clk: sunxi-ng: v3s: Fix TCON clock parents clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name clk: sunxi-ng: v3s: Fix CSI SCLK clock name dt-bindings: clock: mediatek: Add #reset-cells property for MT8188 clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data clk: scmi: Handle case where child clocks are initialized before their parents clk: sunxi-ng: a523: Mark MBUS clock as critical

Merge branch 'clk-pm' into clk-next

2025-07-29T22:19:32Z

* clk-pm: clk: qcom: Remove redundant pm_runtime_mark_last_busy() calls clk: imx: Remove redundant pm_runtime_mark_last_busy() calls Documentation: PM: *_autosuspend() functions update last busy time PM: runtime: Mark last busy stamp in pm_request_autosuspend() PM: runtime: Mark last busy stamp in pm_runtime_autosuspend() PM: runtime: Mark last busy stamp in pm_runtime_put_sync_autosuspend() PM: runtime: Mark last busy stamp in pm_runtime_put_autosuspend() PM: runtime: Document return values of suspend-related API functions

Merge branches 'clk-rockchip', 'clk-thead', 'clk-microchip', 'clk-imx' and 'clk-qcom' into clk-next

2025-07-29T22:19:17Z

* clk-rockchip: clk: rockchip: rk3568: Add PLL rate for 132MHz * clk-thead: clk: thead: th1520-ap: Describe mux clocks with clk_mux clk: thead: th1520-ap: Correctly refer the parent of osc_12m clk: thead: Mark essential bus clocks as CLK_IGNORE_UNUSED * clk-microchip: clk: at91: sam9x7: update pll clk ranges * clk-imx: MAINTAINERS: Update i.MX Clock Entry clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR clk: imx95-blk-ctl: Rename lvds and displaymix csr blk clk: imx95-blk-ctl: Fix synchronous abort dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data * clk-qcom: (65 commits) dt-bindings: clock: qcom,sm4450-dispcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom,sm4450-camcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom,mmcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom,sm8150-camcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom: Remove double colon from description clk: qcom: Add Video Clock controller (VIDEOCC) driver for Milos dt-bindings: clock: qcom: document the Milos Video Clock Controller clk: qcom: Add Graphics Clock controller (GPUCC) driver for Milos dt-bindings: clock: qcom: document the Milos GPU Clock Controller clk: qcom: Add Display Clock controller (DISPCC) driver for Milos dt-bindings: clock: qcom: document the Milos Display Clock Controller clk: qcom: Add Camera Clock controller (CAMCC) driver for Milos dt-bindings: clock: qcom: document the Milos Camera Clock Controller clk: qcom: Add Global Clock controller (GCC) driver for Milos dt-bindings: clock: qcom: document the Milos Global Clock Controller clk: qcom: common: Add support to register rcg dfs in qcom_cc_really_probe clk: qcom: gcc-x1e80100: Add missing video resets dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100 clk: qcom: videocc-sm8550: Allow building without SM8550/SM8560 GCC ...

Merge branches 'clk-renesas', 'clk-samsung', 'clk-spacemit', 'clk-allwinner' and 'clk-amlogic' into clk-next

2025-07-29T22:18:33Z

* clk-renesas: (42 commits) clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs clk: renesas: r9a09g057: Add XSPI clock/reset clk: renesas: r9a09g056: Add XSPI clock/reset clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting clk: renesas: r9a09g057: Add support for xspi mux and divider clk: renesas: r9a09g056: Add support for xspi mux and divider clk: renesas: r9a09g077: Add RIIC module clocks clk: renesas: r9a09g077: Add PLL2 and SDHI clock support clk: renesas: rzv2h: Drop redundant base pointer from pll_clk clk: renesas: r9a09g057: Add entries for the RSPIs dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock clk: renesas: rzv2h: Add missing include file clk: renesas: rzv2h: Use devm_kmemdup_array() clk: renesas: Add CPG/MSSR support to RZ/N2H SoC clk: renesas: r9a09g077: Add PCLKL core clock dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID ... * clk-samsung: clk: samsung: exynosautov920: add block hsi2 clock support dt-bindings: clock: exynosautov920: add hsi2 clock definitions dt-bindings: clock: exynosautov920: sort clock definitions clk: samsung: exynos850: fix a comment clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD * clk-spacemit: clk: spacemit: ccu_pll: fix error return value in recalc_rate callback reset: spacemit: add support for SpacemiT CCU resets clk: spacemit: mark K1 pll1_d8 as critical clk: spacemit: define three reset-only CCUs clk: spacemit: set up reset auxiliary devices soc: spacemit: create a header for clock/reset registers dt-bindings: soc: spacemit: define spacemit,k1-ccu resets * clk-allwinner: clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate() clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll clk: sunxi-ng: v3s: Fix de clock definition clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset * clk-amlogic: clk: amlogic: s4: remove unused data clk: amlogic: drop clk_regmap tables clk: amlogic: get regmap with clk_regmap_init clk: amlogic: remove unnecessary headers clk: amlogic: axg-audio: use the auxiliary reset driver

Merge branches 'clk-bindings', 'clk-cleanup', 'clk-pwm', 'clk-hw-device', 'clk-xilinx' and 'clk-adi' into clk-next

2025-07-29T22:18:13Z

- Support atomic PWMs in the PWM clk driver - clk_hw_get_dev() and clk_hw_get_of_node() helpers * clk-bindings: (30 commits) dt-bindings: clock: convert lpc1850-cgu.txt to yaml format dt-bindings: clock: Convert qca,ath79-pll to DT schema dt-bindings: clock: Convert nuvoton,npcm750-clk to DT schema dt-bindings: clock: Convert moxa,moxart-clock to DT schema dt-bindings: clock: Convert microchip,pic32mzda-clk to DT schema dt-bindings: clock: Convert maxim,max9485 to DT schema dt-bindings: clock: Convert qcom,krait-cc to DT schema dt-bindings: clock: qcom: Remove double colon from description dt-bindings: clock: convert lpc1850-ccu.txt to yaml format dt-bindings: clock: Convert alphascale,asm9260-clock-controller to DT schema dt-bindings: clock: Convert marvell,armada-370-corediv-clock to DT schema dt-bindings: clock: Convert marvell,armada-3700-periph-clock to DT schema dt-bindings: clock: Convert marvell,mvebu-core-clock to DT schema dt-bindings: clock: Convert marvell,berlin2-clk to DT schema dt-bindings: clock: Convert marvell,dove-divider-clock to DT schema dt-bindings: clock: Convert marvell,armada-3700-tbg-clock to DT schema dt-bindings: clock: Convert marvell-armada-370-gating-clock to DT schema dt-bindings: clock: Convert marvell,armada-xp-cpu-clock to DT schema dt-bindings: clock: Convert TI-NSPIRE clocks to DT schema dt-bindings: clock: Convert lsi,axm5516-clks to DT schema ... * clk-cleanup: (29 commits) clk: clocking-wizard: Fix the round rate handling for versal clk: Fix typos clk: tegra: periph: Make tegra_clk_periph_ops static clk: tegra: periph: Fix error handling and resolve unsigned compare warning clk: imx: scu: convert from round_rate() to determine_rate() clk: imx: pllv4: convert from round_rate() to determine_rate() clk: imx: pllv3: convert from round_rate() to determine_rate() clk: imx: pllv2: convert from round_rate() to determine_rate() clk: imx: pll14xx: convert from round_rate() to determine_rate() clk: imx: pfd: convert from round_rate() to determine_rate() clk: imx: frac-pll: convert from round_rate() to determine_rate() clk: imx: fracn-gppll: convert from round_rate() to determine_rate() clk: imx: fixup-div: convert from round_rate() to determine_rate() clk: imx: cpu: convert from round_rate() to determine_rate() clk: imx: busy: convert from round_rate() to determine_rate() clk: imx: composite-93: remove round_rate() in favor of determine_rate() clk: imx: composite-8m: remove round_rate() in favor of determine_rate() clk: bcm: bcm2835: convert from round_rate() to determine_rate() MAINTAINERS: Include clk.py under COMMON CLK FRAMEWORK entry clk: ti: Simplify ti_find_clock_provider() ... * clk-pwm: clk: pwm: Make use of non-sleeping PWMs clk: pwm: Don't reconfigure running PWM at probe time clk: pwm: Convert to use pwm_apply_might_sleep() clk: pwm: Let .get_duty_cycle() return the real duty cycle * clk-hw-device: clk: tests: add clk_hw_get_dev() and clk_hw_get_of_node() tests clk: tests: Make clk_register_clk_parent_data_device_driver() common clk: add a clk_hw helpers to get the clock device or device_node * clk-xilinx: clk: xilinx: vcu: Update vcu init/reset sequence clk: xilinx: vcu: unregister pll_post only if registered correctly * clk-adi: clk: clk-axi-clkgen: fix coding style issues clk: clk-axi-clkgen move to min/max() clk: clk-axi-clkgen: detect axi_clkgen_limits at runtime include: adi-axi-common: add new helper macros include: linux: move adi-axi-common.h out of fpga clk: clk-axi-clkgen: make sure to include mod_devicetable.h clk: clk-axi-clkgen: fix fpfd_max frequency for zynq

Merge tag 'soc-drivers-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2025-07-29T18:13:27Z

Pull SoC driver updates from Arnd Bergmann: "Changes are all over the place, but very little sticks out as noteworthy. There is a new misc driver for the Raspberry Pi 5's RP1 multifunction I/O chip, along with hooking it up to the pinctrl and clk frameworks. The reset controller and memory subsystems have mainly small updates, but there are two new reset drivers for the K230 and VC1800B SoCs, and new memory driver support for Tegra264. The ARM SMCCC and SCMI firmware drivers gain a few more features that should help them be supported across more environments. Similarly, the SoC specific firmware on Tegra and Qualcomm get minor enhancements and chip support. In the drivers/soc/ directory, the ASPEED LPC snoop driver gets an overhaul for code robustness, the Tegra and Qualcomm and NXP drivers grow to support more chips, while the Hisilicon, Mediatek and Renesas drivers see mostly janitorial fixes" * tag 'soc-drivers-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (100 commits) bus: del unnecessary init var soc: fsl: qe: convert set_multiple() to returning an integer pinctrl: rp1: use new GPIO line value setter callbacks soc: hisilicon: kunpeng_hccs: Fix incorrect log information dt-bindings: soc: qcom: qcom,pmic-glink: document Milos compatible dt-bindings: soc: qcom,aoss-qmp: document the Milos Always-On Subsystem side channel dt-bindings: firmware: qcom,scm: document Milos SCM Firmware Interface soc: qcom: socinfo: Add support to retrieve APPSBL build details soc: qcom: pmic_glink: fix OF node leak soc: qcom: spmi-pmic: add more PMIC SUBTYPE IDs soc: qcom: socinfo: Add PM7550 & PMIV0108 PMICs soc: qcom: socinfo: Add SoC IDs for SM7635 family dt-bindings: arm: qcom,ids: Add SoC IDs for SM7635 family firmware: qcom: scm: request the waitqueue irq *after* initializing SCM firmware: qcom: scm: initialize tzmem before marking SCM as available firmware: qcom: scm: take struct device as argument in SHM bridge enable firmware: qcom: scm: remove unused arguments from SHM bridge routines soc: qcom: rpmh-rsc: Add RSC version 4 support memory: tegra: Add Tegra264 MC and EMC support firmware: tegra: bpmp: Fix build failure for tegra264-only config ...