linux/drivers/clk, branch v6.4

clk: pxa: fix NULL pointer dereference in pxa3xx_clk_update_accr

2023-06-15T00:22:17Z

sparse points out an embarrasing bug in an older patch of mine, which uses the register offset instead of an __iomem pointer: drivers/clk/pxa/clk-pxa3xx.c:167:9: sparse: sparse: Using plain integer as NULL pointer Unlike sparse, gcc and clang ignore this bug and fail to warn because a literal '0' is considered a valid representation of a NULL pointer. Fixes: 3c816d950a49 ("ARM: pxa: move clk register definitions to driver") Cc: stable@vger.kernel.org Reported-by: kernel test robot Link: https://lore.kernel.org/oe-kbuild-all/202305111301.RAHohdob-lkp@intel.com/ Signed-off-by: Arnd Bergmann Link: https://lore.kernel.org/r/20230511105845.299859-1-arnd@kernel.org Signed-off-by: Stephen Boyd

clk: clk-loongson2: Zero init clk_init_data

2023-06-13T01:30:46Z

As clk_core_populate_parent_map() checks clk_init_data.num_parents first, and checks clk_init_data.parent_names[] before clk_init_data.parent_data[] and clk_init_data.parent_hws[]. Therefore the clk_init_data structure needs to be explicitly initialised to prevent an unexpected crash if clk_init_data.parent_names[] is a random value. CPU 0 Unable to handle kernel paging request at virtual address 0000000000000dc0, era == 9000000002986290, ra == 900000000298624c Oops[#1]: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 6.4.0-rc2+ #4582 pc 9000000002986290 ra 900000000298624c tp 9000000100094000 sp 9000000100097a60 a0 9000000104541e00 a1 0000000000000000 a2 0000000000000dc0 a3 0000000000000001 a4 90000001000979f0 a5 90000001800977d7 a6 0000000000000000 a7 900000000362a000 t0 90000000034f3548 t1 6f8c2a9cb5ab5f64 t2 0000000000011340 t3 90000000031cf5b0 t4 0000000000000dc0 t5 0000000000000004 t6 0000000000011300 t7 9000000104541e40 t8 000000000005a4f8 u0 9000000104541e00 s9 9000000104541e00 s0 9000000104bc4700 s1 9000000104541da8 s2 0000000000000001 s3 900000000356f9d8 s4 ffffffffffffffff s5 0000000000000000 s6 0000000000000dc0 s7 90000000030d0a88 s8 0000000000000000 ra: 900000000298624c __clk_register+0x228/0x84c ERA: 9000000002986290 __clk_register+0x26c/0x84c CRMD: 000000b0 (PLV0 -IE -DA +PG DACF=CC DACM=CC -WE) PRMD: 00000004 (PPLV0 +PIE -PWE) EUEN: 00000000 (-FPE -SXE -ASXE -BTE) ECFG: 00071c1c (LIE=2-4,10-12 VS=7) ESTAT: 00010000 [PIL] (IS= ECode=1 EsubCode=0) BADV: 0000000000000dc0 PRID: 0014a000 (Loongson-64bit, ) Modules linked in: Process swapper/0 (pid: 1, threadinfo=(____ptrval____), task=(____ptrval____)) Stack : 90000000031c1810 90000000030d0a88 900000000325bac0 90000000034f3548 90000001002ab410 9000000104541e00 0000000000000dc0 9000000003150098 90000000031c1810 90000000031a0460 900000000362a000 90000001002ab410 900000000362a000 9000000104541da8 9000000104541de8 90000001002ab410 900000000362a000 9000000002986a68 90000000034f3ed8 90000000030d0aa8 9000000104541da8 900000000298d3b8 90000000031c1810 0000000000000000 90000000034f3ed8 90000000030d0aa8 0000000000000dc0 90000000030d0a88 90000001002ab410 900000000298d401 0000000000000000 6f8c2a9cb5ab5f64 90000000034f4000 90000000030d0a88 9000000003a48a58 90000001002ab410 9000000104bd81a8 900000000298d484 9000000100020260 0000000000000000 ... Call Trace: [<9000000002986290>] __clk_register+0x26c/0x84c [<9000000002986a68>] devm_clk_hw_register+0x5c/0xe0 [<900000000298d3b8>] loongson2_clk_register.constprop.0+0xdc/0x10c [<900000000298d484>] loongson2_clk_probe+0x9c/0x4ac [<9000000002a4eba4>] platform_probe+0x68/0xc8 [<9000000002a4bf80>] really_probe+0xbc/0x2f0 [<9000000002a4c23c>] __driver_probe_device+0x88/0x128 [<9000000002a4c318>] driver_probe_device+0x3c/0x11c [<9000000002a4c5dc>] __driver_attach+0x98/0x18c [<9000000002a49ca0>] bus_for_each_dev+0x80/0xe0 [<9000000002a4b0dc>] bus_add_driver+0xfc/0x1ec [<9000000002a4d4a8>] driver_register+0x68/0x134 [<90000000020f0110>] do_one_initcall+0x50/0x188 [<9000000003150f00>] kernel_init_freeable+0x224/0x294 [<90000000030240fc>] kernel_init+0x20/0x110 [<90000000020f1568>] ret_from_kernel_thread+0xc/0xa4 Fixes: acc0ccffec50 ("clk: clk-loongson2: add clock controller driver support") Cc: stable@vger.kernel.org Cc: Yinbo Zhu Signed-off-by: Binbin Zhou Link: https://lore.kernel.org/r/20230524014924.2869051-1-zhoubinbin@loongson.cn Signed-off-by: Stephen Boyd

clk: mediatek: mt8365: Fix inverted topclk operations

2023-06-13T01:12:09Z

The given operations are inverted for the wrong registers which makes multiple of the mt8365 hardware units unusable. In my setup at least usb did not work. Fixed by swapping the operations with the inverted ones. Reported-by: Alexandre Mergnat Fixes: 905b7430d3cc ("clk: mediatek: mt8365: Convert simple_gate to mtk_gate clocks") Signed-off-by: Markus Schneider-Pargmann Link: https://lore.kernel.org/r/20230511133226.913600-1-msp@baylibre.com Tested-by: Alexandre Mergnat Reviewed-by: Alexandre Mergnat Reviewed-by: Matthias Brugger Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd

clk: composite: Fix handling of high clock rates

2023-06-13T00:42:10Z

ULONG_MAX is used by a few drivers to figure out the highest available clock rate via clk_round_rate(clk, ULONG_MAX). Since abs() takes a signed value as input, the current logic effectively calculates with ULONG_MAX = -1, which results in the worst parent clock being chosen instead of the best one. For example on Rockchip RK3588 the eMMC driver tries to figure out the highest available clock rate. There are three parent clocks available resulting in the following rate diffs with the existing logic: GPLL: abs(18446744073709551615 - 1188000000) = 1188000001 CPLL: abs(18446744073709551615 - 1500000000) = 1500000001 XIN24M: abs(18446744073709551615 - 24000000) = 24000001 As a result the clock framework will promote a maximum supported clock rate of 24 MHz, even though 1.5GHz are possible. With the updated logic any casting between signed and unsigned is avoided and the numbers look like this instead: GPLL: 18446744073709551615 - 1188000000 = 18446744072521551615 CPLL: 18446744073709551615 - 1500000000 = 18446744072209551615 XIN24M: 18446744073709551615 - 24000000 = 18446744073685551615 As a result the parent with the highest acceptable rate is chosen instead of the parent clock with the lowest one. Cc: stable@vger.kernel.org Fixes: 49502408007b ("mmc: sdhci-of-dwcmshc: properly determine max clock on Rockchip") Tested-by: Christopher Obbard Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20230526171057.66876-2-sebastian.reichel@collabora.com Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd

clk: mediatek: mt8365: Fix index issue

2023-06-12T19:22:03Z

Before the patch [1], the clock probe was done directly in the clk-mt8365 driver. In this probe function, the array which stores the data clocks is sized using the higher defined numbers (*_NR_CLOCK) in the clock lists [2]. Currently, with the patch [1], the specific clk-mt8365 probe function is replaced by the mtk generic one [3], which size the clock data array by adding all the clock descriptor array size provided by the clk-mt8365 driver. Actually, all clock indexes come from the header file [2], that mean, if there are more clock (then more index) in the header file [2] than the number of clock declared in the clock descriptor arrays (which is the case currently), the clock data array will be undersized and then the generic probe function will overflow when it will try to write in "clk_data[CLK_INDEX]". Actually, instead of crashing at boot, the probe function returns an error in the log which looks like: "of_clk_hw_onecell_get: invalid index 135", then this clock isn't enabled. Solve this issue by adding in the driver the missing clocks declared in the header clock file [2]. [1]: Commit ffe91cb28f6a ("clk: mediatek: mt8365: Convert to mtk_clk_simple_{probe,remove}()") [2]: include/dt-bindings/clock/mediatek,mt8365-clk.h [3]: drivers/clk/mediatek/clk-mtk.c Fixes: ffe91cb28f6a ("clk: mediatek: mt8365: Convert to mtk_clk_simple_{probe,remove}()") Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230517-fix-clk-index-v3-1-be4df46065c4@baylibre.com Tested-by: Markus Schneider-Pargmann Reviewed-by: Markus Schneider-Pargmann Signed-off-by: Stephen Boyd

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2023-05-07T17:31:45Z

Pull clk fixes from Stephen Boyd: "A couple more patches that would be good to get into -rc1: - Revert an i.MX patch that's causing video failures because division math goes sideways - Fix a clang + W=1 build isue where FIELD_PREP() is taking a 32-bit variable instead of the usual u64 type - Fix a Kconfig bug in the StarFive JH7110 clk config that selects a reset controller when it can't be selected" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: starfive: Fix RESET_STARFIVE_JH7110 can't be selected in a specified case clk: sp7021: Adjust width of _m in HWM_FIELD_PREP() Revert "clk: imx: composite-8m: Add support to determine_rate"

clk: starfive: Fix RESET_STARFIVE_JH7110 can't be selected in a specified case

2023-05-03T01:34:49Z

When (ARCH_STARFIVE [=n] && COMPILE_TEST [=y] && RESET_CONTROLLER [=n]), RESET_STARFIVE_JH7110 can't be selected by CLK_STARFIVE_JH7110_SYS and CLK_STARFIVE_JH7110_AON. Add a condition `if RESET_CONTROLLER` to fix it. Also, delete redundant selected options of CLK_STARFIVE_JH7110_AON because these options are already selected by the dependency. Fixes: edab7204afe5 ("clk: starfive: Add StarFive JH7110 system clock driver") Fixes: b2ab3c94f41f ("clk: starfive: Add StarFive JH7110 always-on clock driver") Signed-off-by: Hal Feng Link: https://lore.kernel.org/r/20230418123756.62495-2-hal.feng@starfivetech.com Reviewed-by: Conor Dooley Signed-off-by: Stephen Boyd

clk: sp7021: Adjust width of _m in HWM_FIELD_PREP()

2023-05-03T01:34:26Z

When building with clang + W=1, there is a warning around an internal comparison check within the FIELD_PREP() macro, due to a 32-bit variable comparison against ~0ull: drivers/clk/clk-sp7021.c:316:8: error: result of comparison of constant 18446744073709551615 with expression of type 'typeof (_Generic((_m), ...' (aka 'unsigned int') is always false [-Werror,-Wtautological-constant-out-of-range-compare] r0 |= HWM_FIELD_PREP(MASK_SEL_FRA, clk->p[SEL_FRA]); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/clk-sp7021.c:45:15: note: expanded from macro 'HWM_FIELD_PREP' (_m << 16) | FIELD_PREP(_m, value); \ ^~~~~~~~~~~~~~~~~~~~~ include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP' __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/linux/bitfield.h:71:53: note: expanded from macro '__BF_FIELD_CHECK' BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~ note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all) include/linux/compiler_types.h:397:22: note: expanded from macro 'compiletime_assert' _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) ~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/linux/compiler_types.h:385:23: note: expanded from macro '_compiletime_assert' __compiletime_assert(condition, msg, prefix, suffix) ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/linux/compiler_types.h:377:9: note: expanded from macro '__compiletime_assert' if (!(condition)) \ ^~~~~~~~~ This is expected given the types of the input. Increase the size of the temporary variable in HWM_FIELD_PREP() to eliminate the warning, which follows the logic of commit cfd6fb45cfaf ("crypto: ccree - avoid out-of-range warnings from clang") for the same reasons. Signed-off-by: Nathan Chancellor Link: https://lore.kernel.org/r/20230501-sp7021-field_prep-warning-v1-1-5b36d71feefe@kernel.org Reported-by: kernel test robot Link: https://lore.kernel.org/202303221947.pXP2v4xJ-lkp@intel.com/ Reviewed-by: Nick Desaulniers Signed-off-by: Stephen Boyd

Revert "clk: imx: composite-8m: Add support to determine_rate"

2023-05-03T01:22:48Z

This reverts commit 156e96ff2172518b6f83e97d8f11f677bc668e22. This patch was found to cause some division issues on the i.MX8MP which causes the video clocks to not properly divide when division was greate than 8. This causes video failures on disp1_pix and disp2_pix clocks. Until a better solution is found, we'll have to revert this. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20230423123828.1346511-1-aford173@gmail.com Acked-by: Peng Fan Signed-off-by: Stephen Boyd

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2023-04-30T00:29:39Z

Pull clk updates from Stephen Boyd: "Nothing looks out of the ordinary in this batch of clk driver updates. There are a couple patches to the core clk framework, but they're all basically cleanups or debugging aids. The driver updates and new additions are dominated in the diffstat by Qualcomm and MediaTek drivers. Qualcomm gained a handful of new drivers for various SoCs, and MediaTek gained a bunch of drivers for MT8188. The MediaTek drivers are being modernized as well, so there are updates all over that vendor's clk drivers. There's also a couple other new clk drivers in here, for example the Starfive JH7110 SoC support is added. Outside of the two major SoC vendors though, we have the usual collection of non-critical fixes and cleanups to various clk drivers. It's good to see that we're getting more cleanups and modernization patches. Maybe one day we'll be able to properly split clk providers from clk consumers. Core: - Print an informational message before disabling unused clks New Drivers: - BCM63268 timer clock and reset controller - Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and MT8195 SoCs - Mediatek MT8188 SoC clk drivers - Clock driver for Sunplus SP7021 SoC - Clk driver support for Loongson-2 SoCs - Clock driver for Skyworks Si521xx I2C PCIe clock generators - Initial Starfive JH7110 clk/reset support - Global clock controller drivers for Qualcomm SM7150, IPQ9574, MSM8917 and IPQ5332 SoCs - GPU clock controller drivers for SM6115, SM6125, SM6375 and SA8775P SoCs Updates: - Shrink size of clk_fractional_divider a little - Convert various clk drivers to devm_of_clk_add_hw_provider() - Convert platform clk drivers to remove_new() - Converted most Mediatek clock drivers to struct platform_driver - MediaTek clock drivers can be built as modules - Reimplement Loongson-1 clk driver with DT support - Migrate socfpga clk driver to of_clk_add_hw_provider() - Support for i3c clks on Aspeed ast2600 SoCs - Add clock generic devm_clk_hw_register_gate_parent_data - Add audiomix block control for i.MX8MP - Add support for determine_rate to i.MX composite-8m - Let the LCDIF Pixel clock of i.MX8MM and i.MX8MN set parent rate - Provide clock name in error message for clk-gpr-mux on get parent failure - Drop duplicate imx_clk_mux_flags macro - Register the i.MX8MP Media Disp2 Pix clock as bus clock - Add Media LDB root clock to i.MX8MP - Make i.MX8MP nand_usdhc_bus clock as non-critical - Fix the rate table for i.MX fracn-gppll - Disable HW control for the fracn-gppll in order to be controlled by register write - Add support for interger PLL in fracn-gppll - Add mcore_booted module parameter to i.MX93 provider - Add NIC, A55 and ARM PLL clocks to i.MX93 - Fix i.MX8ULP XBAR_DIVBUS and AD_SLOW clock parents - Use "divider closest" clock type for PLL4_PFD dividers on i.MX8ULP to get more accurate clock rates - Mark the MU0_Bi and TPM5 clocks on i.MX8ULP as critical - Update some of the i.MX critical clocks flags to allow glitchless on-the-fly rate change. - Add I2C5 clock on Renesas R-Car V3H - Exynos850: Add CMU_G3D clock controller for the Mali GPU - Extract Exynos5433 (ARM64) clock controller power management code to common driver parts - Exynos850: make PMU_ALIVE_PCLK clock critical - Add Audio, thermal, camera (CSI-2), Image Signal Processor/Channel Selector (ISPCS), and video capture (VIN) clocks on Renesas R-Car V4H - Add video capture (VIN) clocks on Renesas R-Car V3H - Add Cortex-A53 System CPU (Z2) clocks on Renesas R-Car V3M and V3H - Support for Stromer Plus PLL on Qualcomm IPQ5332 - Add a missing reset to Qualcomm QCM2290 - Migrate Qualcomm IPQ4019 to clk_parent_data - Make USB GDSCs enter retention state when disabled on Qualcomm SM6375, MSM8996 and MSM8998 SoCs - Set floor rounding clk_ops for Qualcomm QCM2290 SDCC2 clk - Add two EMAC GDSCs on Qualcomm SC8280XP - Use shared rcg clk ops in Qualcomm SM6115 GCC - Park Qualcomm SM8350 PCIe PIPE clks when disabled - Add GDSCs to Qualcomm SC7280 LPASS audio clock controller - Add missing XO clocks to Qualcomm MSM8226 and MSM8974 - Convert some Qualcomm clk DT bindings to YAML - Reparenting fix for the clock supplying camera modules on Rockchip rk3399 - Mark more critical (bus-)clocks on Rockchip rk3588" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (290 commits) clk: qcom: gcc-sc8280xp: Add EMAC GDSCs clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock drivers clk: rockchip: rk3588: make gate linked clocks critical clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk clk: qcom: add the GPUCC driver for sa8775p dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property clk: starfive: Avoid casting iomem pointers clk: microchip: fix potential UAF in auxdev release callback clk: qcom: rpm: Use managed `of_clk_add_hw_provider()` clk: mediatek: fhctl: Mark local variables static clk: sifive: make SiFive clk drivers depend on ARCH_ symbols clk: uniphier: Use managed `of_clk_add_hw_provider()` clk: si5351: Use managed `of_clk_add_hw_provider()` clk: si570: Use managed `of_clk_add_hw_provider()` clk: si514: Use managed `of_clk_add_hw_provider()` clk: lmk04832: Use managed `of_clk_add_hw_provider()` ...