linux/drivers/clocksource, branch v5.17

ARM: dts: Use 32KiHz oscillator on devkit8000

2022-02-18T08:08:45Z

Devkit8000 board seems to always used 32k_counter as clocksource. Restore this behavior. If clocksource is back to 32k_counter, timer12 is now the clockevent source (as before) and timer2 is not longer needed here. This commit fixes the same issue observed with commit 23885389dbbb ("ARM: dts: Fix timer regression for beagleboard revision c") when sleep is blocked until hitting keys over serial console. Fixes: aba1ad05da08 ("clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support") Fixes: e428e250fde6 ("ARM: dts: Configure system timers for omap3") Signed-off-by: Anthoine Bourgeois Signed-off-by: Tony Lindgren

Merge tag 'omap-for-v5.17/fixes-for-merge-window-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes

2022-02-07T16:42:44Z

Fixes for omaps A series of fixes for omap variants for minor issues, and a fix for a timer regression for some omap3 beagleboard versions. The timer fix needs to patch both the dts and the timer code because otherwise the timer quirk handling for old dtbs will prevent the dts fix from working. The other changes are for issues found by automated analysis, a macasp typo fix, and two cosmetic fixes for clocks. * tag 'omap-for-v5.17/fixes-for-merge-window-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: Don't use legacy clock defines for dra7 clkctrl clk: ti: Move dra7 clock devices out of the legacy section ARM: dts: Fix timer regression for beagleboard revision c ARM: dts: am335x-wega: Fix typo in mcasp property rx-num-evt ARM: OMAP2+: adjust the location of put_device() call in omapdss_init_of ARM: OMAP2+: hwmod: Add of_node_put() before break Link: https://lore.kernel.org/r/pull-1641801310-149268@atomide.com Signed-off-by: Arnd Bergmann

Merge tag 'timers-v5.17-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core

2022-01-10T12:53:16Z

Pull clocksource/events updates from Daniel Lezcano: - Refactor resource allocation on the Exynos_mct driver without functional changes (Marek Szyprowski) - Add imx8ulp compatible string for NPX TPM driver (Jacky Bai) - Fix comma introduced by error by replacing it by the initial semicolon on the Exynos_mct (Will Deacon) - Add OSTM driver support on Renesas. The reset line must be deasserted before accessing the registers. This change depends on an external change resulting in a shared immutable branch 'reset/of-get-optional-exclusive' from git://git.pengutronix.de/pza/linux (Biju Das) - Make the OSTM Kconfig option visible to user in order to let him disable it when ARM architected timers is enabled (Biju Das) - Tag two variables on iMX sysctr _ro_afterinit (Peng Fan) - Set the cpumask to cpu_possible_mask in order to have full benefit of the DYNIRQ flag on iMX sysctr (Peng Fan) - Tag __maybe_unused a variable in the Pistachio timer driver in order to fix a warning reported by the kernel test robot (Drew Fustini) - Add MStar MSC313e timer support and the ssd20xd-based variant, as well as the DT bindings (Romain Perier) - Remove the incompatible compatible string for the rk3066 (Johan Jonker) - Fix dts_check warnings on the cadence ttc driver by adding the power domain bindings (Michal Simek) Link: https://lore.kernel.org/lkml/e093c706-c98d-29ee-0102-78b6d41c6164@linaro.org

clocksource/drivers/msc313e: Add support for ssd20xd-based platforms

2021-12-20T12:28:39Z

On SSD20X family SoCs the timers are connected to a 432MHz clock instead of 12MHz that all the previous chips used. There is no way to reduce or divide these clocks in the clktree yet as we do not know exactly where the 432MHz clock comes from but it is enabled at boot. The SSD20X timers have an input clock divider within the timer itself to configure the frequency. timer0 is preconfigured at power up to run at 12MHz so it is backwards compatible and doesn't need special handling right now. timer1 and timer2 run at 432Mhz at power up so are not backward compatible. This commit adds support for the input clock divider register and sets timer1 and timer2 to run at 48Mhz for clockevents. Signed-off-by: Romain Perier Link: https://lore.kernel.org/r/20211217195727.8955-3-romain.perier@gmail.com Signed-off-by: Daniel Lezcano

clocksource/drivers: Add MStar MSC313e timer support

2021-12-20T12:28:28Z

The MSC313e-compatible SoCs have 3 timer hardware blocks. All of these are free running 32-bit increasing counters and can generate interrupts. Based onto a maximum value register, each timer can either count from 0 to max, one time then stop (which generates interrupts) or can count from 0 to max and then roll. This commit adds basic support for these timers, the first timer block being used as clocksource/sched_clock and delay, while the others will be used as clockevents. Signed-off-by: Romain Perier Co-developed-by: Daniel Palmer Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20211217195727.8955-2-romain.perier@gmail.com Signed-off-by: Daniel Lezcano

ARM: dts: Fix timer regression for beagleboard revision c

2021-12-17T12:15:43Z

Commit e428e250fde6 ("ARM: dts: Configure system timers for omap3") caused a timer regression for beagleboard revision c where the system clockevent stops working if omap3isp module is unloaded. Turns out we still have beagleboard revisions a-b4 capacitor c70 quirks applied that limit the usable timers for no good reason. This also affects the power management as we use the system clock instead of the 32k clock source. Let's fix the issue by adding a new omap3-beagle-ab4.dts for the old timer quirks. This allows us to remove the timer quirks for later beagleboard revisions. We also need to update the related timer quirk check for the correct compatible property. Fixes: e428e250fde6 ("ARM: dts: Configure system timers for omap3") Cc: linux-kernel@vger.kernel.org Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: Rob Herring Reported-by: Jarkko Nikula Tested-by: Jarkko Nikula Signed-off-by: Tony Lindgren

clocksource/drivers/pistachio: Fix -Wunused-but-set-variable warning

2021-12-14T09:17:36Z

Variable 'overflow' set but not used, but this is the intended behavior. The hardware only updates the counter register after the overflow register read. However, the value of overflow is not actually needed. Link: https://lore.kernel.org/lkml/202111200402.afQsussU-lkp@intel.com/ Reported-by: kernel test robot Suggested-by: Daniel Lezcano Signed-off-by: Drew Fustini Link: https://lore.kernel.org/r/20211123192524.1038304-1-dfustini@baylibre.com Signed-off-by: Daniel Lezcano

clocksource/drivers/timer-imx-sysctr: Set cpumask to cpu_possible_mask

2021-12-14T09:17:27Z

The syctr interrupt could set the affinity to any cores in the SoC. However, the default affinity is set to cpu 0. This timer will be used as broadcast timer on all the i.MX SoCs. Because DYNIRQ flag is set, the core time framework will runtime set the interrupt affinity to the cores that needs to wake up and the cpumask will runtime set to the core that will be wake up. So even the sysctr initialization use cpumask 0, there is no issue, the current patch is just use cpu_possible_mask to show the fact that the timer supports routed to all the cpu cores and nothing else. Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20211201125030.2307746-2-peng.fan@oss.nxp.com Signed-off-by: Daniel Lezcano

clocksource/drivers/arm_arch_timer: Force inlining of erratum_set_next_event_generic()

2021-12-10T16:47:00Z

With some specific kernel configuration and Clang, the kernel fails to like with something like: ld.lld: error: undefined symbol: __compiletime_assert_200 >>> referenced by arch_timer.h:156 (./arch/arm64/include/asm/arch_timer.h:156) >>> clocksource/arm_arch_timer.o:(erratum_set_next_event_generic) in archive drivers/built-in.a ld.lld: error: undefined symbol: __compiletime_assert_197 >>> referenced by arch_timer.h:133 (./arch/arm64/include/asm/arch_timer.h:133) >>> clocksource/arm_arch_timer.o:(erratum_set_next_event_generic) in archive drivers/built-in.a make: *** [Makefile:1161: vmlinux] Error 1 These are due to the BUILD_BUG() macros contained in the low-level accessors (arch_timer_reg_{write,read}_cp15) being emitted, as the access type wasn't known at compile time. Fix this by making erratum_set_next_event_generic() __force_inline, resulting in the 'access' parameter to be resolved at compile time, similarly to what is already done for set_next_event(). Fixes: 4775bc63f880 ("Add build-time guards for unhandled register accesses") Reported-by: Greg Kroah-Hartman Signed-off-by: Marc Zyngier Cc: Mark Rutland Cc: Daniel Lezcano Cc: Sami Tolvanen Cc: Nick Desaulniers Tested-by: Sami Tolvanen Reviewed-by: Nathan Chancellor Tested-by: Nathan Chancellor Link: https://lore.kernel.org/r/20211117113532.3895208-1-maz@kernel.org Signed-off-by: Daniel Lezcano

clocksource/drivers/dw_apb_timer_of: Fix probe failure

2021-12-10T16:46:54Z

The driver refuses to probe with -EINVAL since the commit 5d9814df0aec ("clocksource/drivers/dw_apb_timer_of: Add error handling if no clock available"). Before the driver used to probe successfully if either "clock-freq" or "clock-frequency" properties has been specified in the device tree. That commit changed if (A && B) panic("No clock nor clock-frequency property"); into if (!A && !B) return 0; That's a bug: the reverse of `A && B` is '!A || !B', not '!A && !B' Signed-off-by: Vadim V. Vlasov Signed-off-by: Alexey Sheplyakov Fixes: 5d9814df0aec56a6 ("clocksource/drivers/dw_apb_timer_of: Add error handling if no clock available"). Cc: Daniel Lezcano Cc: Dinh Nguyen Cc: Thomas Gleixner Cc: Vadim V. Vlasov Acked-by: Dinh Nguyen Link: https://lore.kernel.org/r/20211109153401.157491-1-asheplyakov@basealt.ru Signed-off-by: Daniel Lezcano