<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/clocksource, branch v5.8</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.8</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.8'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-07-25T20:27:12Z</updated>
<entry>
<title>Merge tag 'timers-urgent-2020-07-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into master</title>
<updated>2020-07-25T20:27:12Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-07-25T20:27:12Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a7b36c2b134f7ca75789d174b97d07acccbf6b93'/>
<id>urn:sha1:a7b36c2b134f7ca75789d174b97d07acccbf6b93</id>
<content type='text'>
Pull timer fix from Ingo Molnar:
 "Fix a suspend/resume regression (crash) on TI AM3/AM4 SoC's"

* tag 'timers-urgent-2020-07-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  clocksource/drivers/timer-ti-dm: Fix suspend and resume for am3 and am4
</content>
</entry>
<entry>
<title>clocksource/drivers/timer-ti-dm: Fix suspend and resume for am3 and am4</title>
<updated>2020-07-21T13:48:33Z</updated>
<author>
<name>Tony Lindgren</name>
<email>tony@atomide.com</email>
</author>
<published>2020-07-13T16:26:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6cfcd5563b4fadbf49ba8fa481978e5e86d30322'/>
<id>urn:sha1:6cfcd5563b4fadbf49ba8fa481978e5e86d30322</id>
<content type='text'>
Carlos Hernandez &lt;ceh@ti.com&gt; reported that we now have a suspend and
resume regresssion on am3 and am4 compared to the earlier kernels. While
suspend and resume works with v5.8-rc3, we now get errors with rtcwake:

pm33xx pm33xx: PM: Could not transition all powerdomains to target state
...
rtcwake: write error

This is because we now fail to idle the system timer clocks that the
idle code checks and the error gets propagated to the rtcwake.

Turns out there are several issues that need to be fixed:

1. Ignore no-idle and no-reset configured timers for the ti-sysc
   interconnect target driver as otherwise it will keep the system timer
   clocks enabled

2. Toggle the system timer functional clock for suspend for am3 and am4
   (but not for clocksource on am3)

3. Only reconfigure type1 timers in dmtimer_systimer_disable()

4. Use of_machine_is_compatible() instead of of_device_is_compatible()
   for checking the SoC type

Fixes: 52762fbd1c47 ("clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support")
Reported-by: Carlos Hernandez &lt;ceh@ti.com&gt;
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
Tested-by: Carlos Hernandez &lt;ceh@ti.com&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Link: https://lore.kernel.org/r/20200713162601.6829-1-tony@atomide.com
</content>
</entry>
<entry>
<title>arm64: arch_timer: Disable the compat vdso for cores affected by ARM64_WORKAROUND_1418040</title>
<updated>2020-07-08T20:57:51Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-07-06T16:38:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4b661d6133c5d3a7c9aca0b4ee5a78c7766eff3f'/>
<id>urn:sha1:4b661d6133c5d3a7c9aca0b4ee5a78c7766eff3f</id>
<content type='text'>
ARM64_WORKAROUND_1418040 requires that AArch32 EL0 accesses to
the virtual counter register are trapped and emulated by the kernel.
This makes the vdso pretty pointless, and in some cases livelock
prone.

Provide a workaround entry that limits the vdso to 64bit tasks.

Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Acked-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20200706163802.1836732-4-maz@kernel.org
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: arch_timer: Allow an workaround descriptor to disable compat vdso</title>
<updated>2020-07-08T20:57:51Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-07-06T16:38:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c1fbec4ac0d701f350a581941d35643d5a9cd184'/>
<id>urn:sha1:c1fbec4ac0d701f350a581941d35643d5a9cd184</id>
<content type='text'>
As we are about to disable the vdso for compat tasks in some circumstances,
let's allow a workaround descriptor to express exactly that.

Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Acked-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20200706163802.1836732-3-maz@kernel.org
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>clocksource/drivers/timer-riscv: Use per-CPU timer interrupt</title>
<updated>2020-06-10T02:11:22Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-06-01T09:15:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=033a65de7eced89f62d2cd166b1ee2d33af4f1e4'/>
<id>urn:sha1:033a65de7eced89f62d2cd166b1ee2d33af4f1e4</id>
<content type='text'>
Instead of directly calling RISC-V timer interrupt handler from
RISC-V local interrupt conntroller driver, this patch implements
RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
of Linux IRQ subsystem.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Reviewed-by: Marc Zyngier &lt;maz@kernel.org&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
</content>
</entry>
<entry>
<title>clocksource/drivers/timer-versatile: Clear OF_POPULATED flag</title>
<updated>2020-05-22T22:03:25Z</updated>
<author>
<name>Saravana Kannan</name>
<email>saravanak@google.com</email>
</author>
<published>2020-03-24T19:53:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7a3768c206a006525afc090f92d4d618d8356b92'/>
<id>urn:sha1:7a3768c206a006525afc090f92d4d618d8356b92</id>
<content type='text'>
The commit 4f41fe386a94 ("clocksource/drivers/timer-probe: Avoid
creating dead devices") broke the handling of arm,vexpress-sysreg [1].

The arm,vexpress-sysreg device is handled by both timer-versatile.c and
drivers/mfd/vexpress-sysreg.c. While the timer driver doesn't use the
device, the mfd driver still needs a device to probe.

So, this patch clears the OF_POPULATED flag to continue creating the
device.

[1] - https://lore.kernel.org/lkml/20200324175955.GA16972@arm.com/

Fixes: 4f41fe386a94 ("clocksource/drivers/timer-probe: Avoid creating dead devices")
Signed-off-by: Saravana Kannan &lt;saravanak@google.com&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Link: https://lore.kernel.org/r/20200324195302.203115-1-saravanak@google.com
</content>
</entry>
<entry>
<title>clocksource: mips-gic-timer: Mark GIC timer as unstable if ref clock changes</title>
<updated>2020-05-22T22:03:16Z</updated>
<author>
<name>Serge Semin</name>
<email>Sergey.Semin@baikalelectronics.ru</email>
</author>
<published>2020-05-21T20:48:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7d7de1a65349811b24971c5e8e040e6aac192dd4'/>
<id>urn:sha1:7d7de1a65349811b24971c5e8e040e6aac192dd4</id>
<content type='text'>
Currently clocksource framework doesn't support the clocks with variable
frequency. Since MIPS GIC timer ticks rate might be unstable on some
platforms, we must make sure that it justifies the clocksource
requirements. MIPS GIC timer is incremented with the CPU cluster reference
clocks rate. So in case if CPU frequency changes, the MIPS GIC tick rate
changes synchronously. Due to this the clocksource subsystem can't rely on
the timer to measure system clocks anymore. This commit marks the MIPS GIC
based clocksource as unstable if reference clock (normally it's a CPU
reference clocks) rate changes. The clocksource will execute a watchdog
thread, which lowers the MIPS GIC timer rating to zero and fallbacks to a
new stable one.

Note we don't need to set the CLOCK_SOURCE_MUST_VERIFY flag to the MIPS
GIC clocksource since normally the timer is stable. The only reason why
it gets unstable is due to the ref clock rate change, which event we
detect here in the driver by means of the clocks event notifier.

Signed-off-by: Serge Semin &lt;Sergey.Semin@baikalelectronics.ru&gt;
Cc: Alexey Malahov &lt;Alexey.Malahov@baikalelectronics.ru&gt;
Cc: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
Cc: Paul Burton &lt;paulburton@kernel.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Alessandro Zummo &lt;a.zummo@towertech.it&gt;
Cc: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: Rob Herring &lt;robh+dt@kernel.org&gt;
Cc: linux-mips@vger.kernel.org
Cc: linux-rtc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Link: https://lore.kernel.org/r/20200521204818.25436-9-Sergey.Semin@baikalelectronics.ru
</content>
</entry>
<entry>
<title>clocksource: mips-gic-timer: Register as sched_clock</title>
<updated>2020-05-22T22:03:08Z</updated>
<author>
<name>Paul Burton</name>
<email>paulburton@kernel.org</email>
</author>
<published>2020-05-21T20:48:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=48016e78d328998b1f00bcfb639adeabca51abe5'/>
<id>urn:sha1:48016e78d328998b1f00bcfb639adeabca51abe5</id>
<content type='text'>
The MIPS GIC timer is well suited for use as sched_clock, so register it
as such.

Whilst the existing gic_read_count() function matches the prototype
needed by sched_clock_register() already, we split it into 2 functions
in order to remove the need to evaluate the mips_cm_is64 condition
within each call since sched_clock should be as fast as possible.

Note the sched clock framework needs the clock source being stable in
order to rely on it. So we register the MIPS GIC timer as schedule clocks
only if it's, if either the system doesn't have CPU-frequency enabled or
the CPU frequency is changed by means of the CPC core clock divider
available on the platforms with CM3 or newer.

Signed-off-by: Paul Burton &lt;paulburton@kernel.org&gt;
Co-developed-by: Serge Semin &lt;Sergey.Semin@baikalelectronics.ru&gt;
[Sergey.Semin@baikalelectronics.ru: Register sched-clock if CM3 or !CPU-freq]
Signed-off-by: Serge Semin &lt;Sergey.Semin@baikalelectronics.ru&gt;
Cc: Alexey Malahov &lt;Alexey.Malahov@baikalelectronics.ru&gt;
Cc: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Alessandro Zummo &lt;a.zummo@towertech.it&gt;
Cc: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: Rob Herring &lt;robh+dt@kernel.org&gt;
Cc: linux-mips@vger.kernel.org
Cc: linux-rtc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Link: https://lore.kernel.org/r/20200521204818.25436-8-Sergey.Semin@baikalelectronics.ru
</content>
</entry>
<entry>
<title>clocksource: dw_apb_timer_of: Fix missing clockevent timers</title>
<updated>2020-05-22T22:02:59Z</updated>
<author>
<name>Serge Semin</name>
<email>Sergey.Semin@baikalelectronics.ru</email>
</author>
<published>2020-05-21T20:48:15Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6d2e16a3181bafb77b535095c39ad1c8b9558c8c'/>
<id>urn:sha1:6d2e16a3181bafb77b535095c39ad1c8b9558c8c</id>
<content type='text'>
Commit 100214889973 ("clocksource: dw_apb_timer_of: use
clocksource_of_init") replaced a publicly available driver
initialization method with one called by the timer_probe() method
available after CLKSRC_OF. In current implementation it traverses
all the timers available in the system and calls their initialization
methods if corresponding devices were either in dtb or in acpi. But
if before the commit any number of available timers would be installed
as clockevent and clocksource devices, after that there would be at most
two. The rest are just ignored since default case branch doesn't do
anything. I don't see a reason of such behaviour, neither the commit
message explains it. Moreover this might be wrong if on some platforms
these timers might be used for different purpose, as virtually CPU-local
clockevent timers and as an independent broadcast timer. So in order
to keep the compatibility with the platforms where the order of the
timers detection has some meaning, lets add the secondly discovered
timer to be of clocksource/sched_clock type, while the very first and
the others would provide the clockevents service.

Fixes: 100214889973 ("clocksource: dw_apb_timer_of: use clocksource_of_init")
Signed-off-by: Serge Semin &lt;Sergey.Semin@baikalelectronics.ru&gt;
Cc: Alexey Malahov &lt;Alexey.Malahov@baikalelectronics.ru&gt;
Cc: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
Cc: Paul Burton &lt;paulburton@kernel.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Alessandro Zummo &lt;a.zummo@towertech.it&gt;
Cc: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: Rob Herring &lt;robh+dt@kernel.org&gt;
Cc: linux-mips@vger.kernel.org
Cc: linux-rtc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Link: https://lore.kernel.org/r/20200521204818.25436-7-Sergey.Semin@baikalelectronics.ru
</content>
</entry>
<entry>
<title>clocksource: dw_apb_timer: Affiliate of-based timer with any CPU</title>
<updated>2020-05-22T22:02:50Z</updated>
<author>
<name>Serge Semin</name>
<email>Sergey.Semin@baikalelectronics.ru</email>
</author>
<published>2020-05-21T20:48:14Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=65e0f876405ef4f0ff25eb1c5ff3e9b536d68805'/>
<id>urn:sha1:65e0f876405ef4f0ff25eb1c5ff3e9b536d68805</id>
<content type='text'>
Currently any DW APB Timer device detected in OF is bound to CPU #0.
Doing so is redundant since DW APB Timer isn't CPU-local timer, but as
having APB interface is normally accessible from any CPU in the system. By
artificially affiliating the DW timer to the very first CPU we may and in
our case will make the clockevent subsystem to decline the more performant
real CPU-local timers selection in favor of in fact non-local and
accessible over a slow bus - DW APB Timers.

Let's not affiliate the of-detected DW APB Timers to any CPU. By doing so
the clockevent framework would prefer to select the real CPU-local timer
instead of DW APB one. Otherwise if there is no other than DW APB device
for clockevents tracking then it will be selected.

Signed-off-by: Serge Semin &lt;Sergey.Semin@baikalelectronics.ru&gt;
Cc: Alexey Malahov &lt;Alexey.Malahov@baikalelectronics.ru&gt;
Cc: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
Cc: Paul Burton &lt;paulburton@kernel.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Alessandro Zummo &lt;a.zummo@towertech.it&gt;
Cc: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: Rob Herring &lt;robh+dt@kernel.org&gt;
Cc: linux-mips@vger.kernel.org
Cc: linux-rtc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Link: https://lore.kernel.org/r/20200521204818.25436-6-Sergey.Semin@baikalelectronics.ru
</content>
</entry>
</feed>
