<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/dma/ipu, branch v3.0</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v3.0</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v3.0'/>
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<updated>2011-03-25T21:09:00Z</updated>
<entry>
<title>dma: Ipu: Convert interupt code</title>
<updated>2011-03-25T21:09:00Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2011-03-25T11:21:38Z</published>
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<id>urn:sha1:6a03513825db4db57fa93821a0c04dbbb39a68e6</id>
<content type='text'>
Convert to the new irq chip functions and cleanup the name space.

[ Guennadi reported: irq_data_get_chip_data is undefined. Yes, I screwed up. 
 it needs to be irq_data_get_irq_chip_data ]

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Tested-by: Guennadi Liakhovetski &lt;g.liakhovetski@gmx.de&gt;
Cc: Dan Williams &lt;dan.j.williams@intel.com&gt;
LKML-Reference: &lt;alpine.LFD.2.00.1103251220000.31464@localhost6.localdomain6&gt;
</content>
</entry>
<entry>
<title>dma: ipu_idmac: do not lose valid received data in the irq handler</title>
<updated>2011-02-14T10:28:16Z</updated>
<author>
<name>Anatolij Gustschin</name>
<email>agust@denx.de</email>
</author>
<published>2011-01-31T12:22:29Z</published>
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<id>urn:sha1:a646bd7f0824d3e0f02ff8d7410704f965de01bc</id>
<content type='text'>
Currently when two or more buffers are queued by the camera driver
and so the double buffering is enabled in the idmac, we lose one
frame comming from CSI since the reporting of arrival of the first
frame is deferred by the DMAIC_7_EOF interrupt handler and reporting
of the arrival of the last frame is not done at all. So when requesting
N frames from the image sensor we actually receive N - 1 frames in
user space.

The reason for this behaviour is that the DMAIC_7_EOF interrupt
handler misleadingly assumes that the CUR_BUF flag is pointing to the
buffer used by the IDMAC. Actually it is not the case since the
CUR_BUF flag will be flipped by the FSU when the FSU is sending the
&lt;TASK&gt;_NEW_FRM_RDY signal when new frame data is delivered by the CSI.
When sending this singal, FSU updates the DMA_CUR_BUF and the
DMA_BUFx_RDY flags: the DMA_CUR_BUF is flipped, the DMA_BUFx_RDY
is cleared, indicating that the frame data is beeing written by
the IDMAC to the pointed buffer. DMA_BUFx_RDY is supposed to be
set to the ready state again by the MCU, when it has handled the
received data. DMAIC_7_CUR_BUF flag won't be flipped here by the
IPU, so waiting for this event in the EOF interrupt handler is wrong.
Actually there is no spurious interrupt as described in the comments,
this is the valid DMAIC_7_EOF interrupt indicating reception of the
frame from CSI.

The patch removes code that waits for flipping of the DMAIC_7_CUR_BUF
flag in the DMAIC_7_EOF interrupt handler. As the comment in the
current code denotes, this waiting doesn't help anyway. As a result
of this removal the reporting of the first arrived frame is not
deferred to the time of arrival of the next frame and the drivers
software flag 'ichan-&gt;active_buffer' is in sync with DMAIC_7_CUR_BUF
flag, so the reception of all requested frames works.

This has been verified on the hardware which is triggering the
image sensor by the programmable state machine, allowing to
obtain exact number of frames. On this hardware we do not tolerate
losing frames.

This patch also removes resetting the DMA_BUFx_RDY flags of
all channels in ipu_disable_channel() since transfers on other
DMA channels might be triggered by other running tasks and the
buffers should always be ready for data sending or reception.

Signed-off-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Reviewed-by: Guennadi Liakhovetski &lt;g.liakhovetski@gmx.de&gt;
Tested-by: Guennadi Liakhovetski &lt;g.liakhovetski@gmx.de&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>DMAENGINE: extend the control command to include an arg</title>
<updated>2010-05-17T23:30:42Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@stericsson.com</email>
</author>
<published>2010-05-17T23:30:42Z</published>
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<id>urn:sha1:058276303dbc4ed089c1f7dad0871810b1f5ddf1</id>
<content type='text'>
This adds an argument to the DMAengine control function, so that
we can later provide control commands that need some external data
passed in through an argument akin to the ioctl() operation
prototype.

[dan.j.williams@intel.com: fix up some missed conversions]
Signed-off-by: Linus Walleij &lt;linus.walleij@stericsson.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: provide helper for setting txstate</title>
<updated>2010-03-26T23:52:10Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2010-03-26T23:52:10Z</published>
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<id>urn:sha1:bca3469205402d9fb14060d255d8786ae2256640</id>
<content type='text'>
Simple conditional struct filler to cut out some duplicated code.

Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>DMAENGINE: generic channel status v2</title>
<updated>2010-03-26T23:50:49Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@stericsson.com</email>
</author>
<published>2010-03-26T23:50:49Z</published>
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<id>urn:sha1:0793448187643b50af89d36b08470baf45a3cab4</id>
<content type='text'>
Convert the device_is_tx_complete() operation on the
DMA engine to a generic device_tx_status()operation which
can return three states, DMA_TX_RUNNING, DMA_TX_COMPLETE,
DMA_TX_PAUSED.

[dan.j.williams@intel.com: update for timberdale]
Signed-off-by: Linus Walleij &lt;linus.walleij@stericsson.com&gt;
Acked-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
Cc: Maciej Sosnowski &lt;maciej.sosnowski@intel.com&gt;
Cc: Nicolas Ferre &lt;nicolas.ferre@atmel.com&gt;
Cc: Pavel Machek &lt;pavel@ucw.cz&gt;
Cc: Li Yang &lt;leoli@freescale.com&gt;
Cc: Guennadi Liakhovetski &lt;g.liakhovetski@gmx.de&gt;
Cc: Paul Mundt &lt;lethal@linux-sh.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Haavard Skinnemoen &lt;haavard.skinnemoen@atmel.com&gt;
Cc: Magnus Damm &lt;damm@opensource.se&gt;
Cc: Liam Girdwood &lt;lrg@slimlogic.co.uk&gt;
Cc: Joe Perches &lt;joe@perches.com&gt;
Cc: Roland Dreier &lt;rdreier@cisco.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>DMAENGINE: generic slave control v2</title>
<updated>2010-03-26T23:44:01Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@stericsson.com</email>
</author>
<published>2010-03-26T23:44:01Z</published>
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<id>urn:sha1:c3635c78e500a52c9fcd55de381a72928d9e054d</id>
<content type='text'>
Convert the device_terminate_all() operation on the
DMA engine to a generic device_control() operation
which can now optionally support also pausing and
resuming DMA on a certain channel. Implemented for the
COH 901 318 DMAC as an example.

[dan.j.williams@intel.com: update for timberdale]
Signed-off-by: Linus Walleij &lt;linus.walleij@stericsson.com&gt;
Acked-by: Mark Brown &lt;broonie@opensource.wolfsonmicro.com&gt;
Cc: Maciej Sosnowski &lt;maciej.sosnowski@intel.com&gt;
Cc: Nicolas Ferre &lt;nicolas.ferre@atmel.com&gt;
Cc: Pavel Machek &lt;pavel@ucw.cz&gt;
Cc: Li Yang &lt;leoli@freescale.com&gt;
Cc: Guennadi Liakhovetski &lt;g.liakhovetski@gmx.de&gt;
Cc: Paul Mundt &lt;lethal@linux-sh.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Haavard Skinnemoen &lt;haavard.skinnemoen@atmel.com&gt;
Cc: Magnus Damm &lt;damm@opensource.se&gt;
Cc: Liam Girdwood &lt;lrg@slimlogic.co.uk&gt;
Cc: Joe Perches &lt;joe@perches.com&gt;
Cc: Roland Dreier &lt;rdreier@cisco.com&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'coh' into dmaengine</title>
<updated>2010-03-04T04:22:21Z</updated>
<author>
<name>Dan Williams</name>
<email>dan.j.williams@intel.com</email>
</author>
<published>2010-03-04T04:22:21Z</published>
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<id>urn:sha1:dd58ffcf5a5352fc10820c8ffbcd5fed416a2c3a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>async-tx: fix buffer submission error handling in ipu_idma.c</title>
<updated>2010-02-10T19:01:06Z</updated>
<author>
<name>Guennadi Liakhovetski</name>
<email>g.liakhovetski@gmx.de</email>
</author>
<published>2010-02-10T16:32:38Z</published>
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<id>urn:sha1:8f98781e0f15207b6ab33bee1fae05428be0475b</id>
<content type='text'>
If submitting new buffer failed, a wrong descriptor gets completed and it
doesn't check, if a callback is at all defined, which can lead to an Oops. Fix
these bugs and make ipu_update_channel_buffer() void, because it never fails.

Signed-off-by: Guennadi Liakhovetski &lt;g.liakhovetski@gmx.de&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>dma: cases IPU_PIX_FMT_BGRA32, BGR32 and ABGR32 are the same in ipu_ch_param_set_size()</title>
<updated>2010-02-03T06:42:25Z</updated>
<author>
<name>Roel Kluin</name>
<email>roel.kluin@gmail.com</email>
</author>
<published>2010-01-20T00:25:56Z</published>
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<id>urn:sha1:9ad7bd2944bd979ef4877cd439719be44c5f3b47</id>
<content type='text'>
In these cases the same statements are executed.

Signed-off-by: Roel Kluin &lt;roel.kluin@gmail.com&gt;
Acked-by: Guennadi Liakhovetski &lt;g.liakhovetski@gmx.de&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
<entry>
<title>dma: fix ipu_idmac.c to not discard the last queued buffer</title>
<updated>2009-05-12T21:41:48Z</updated>
<author>
<name>Guennadi Liakhovetski</name>
<email>g.liakhovetski@gmx.de</email>
</author>
<published>2009-05-12T07:16:29Z</published>
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<id>urn:sha1:ad567ffb32f067b30606071eb568cf637fe42185</id>
<content type='text'>
This also fixes the case of a single queued buffer, for example, when taking a
single frame snapshot with the mx3_camera driver.

Reported-by: Agustin Ferrin Pozuelo &lt;gatoguan-os@yahoo.com&gt;
Tested-by: Agustin Ferrin Pozuelo &lt;gatoguan-os@yahoo.com&gt;
Signed-off-by: Guennadi Liakhovetski &lt;g.liakhovetski@gmx.de&gt;
Signed-off-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
</content>
</entry>
</feed>
