<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/Makefile, branch v5.10</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.10</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.10'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-08-14T20:22:41Z</updated>
<entry>
<title>drm/amd/pm: optimize the power related source code layout</title>
<updated>2020-08-14T20:22:41Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-08-13T08:39:25Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e098bc9612c2b60f94920461d71c92962a916e73'/>
<id>urn:sha1:e098bc9612c2b60f94920461d71c92962a916e73</id>
<content type='text'>
The target is to provide a clear entry point(for power routines).
Also this can help to maintain a clear view about the frameworks
used on different ASICs. Hopefully all these can make power part
more friendly to play with.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add debugfs interface for RAP test</title>
<updated>2020-08-14T20:22:40Z</updated>
<author>
<name>Wenhui Sheng</name>
<email>Wenhui.Sheng@amd.com</email>
</author>
<published>2020-08-11T03:02:03Z</published>
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<id>urn:sha1:a4322e1881bed80ddb904482f0b2e948fa7fd47e</id>
<content type='text'>
After amdgpu driver loading successfully, we can use
RAP debugfs interface &lt;debugfs_dir&gt;/dri/xxx/rap_test
to trigger RAP test.

Currently only L0 validate test is supported.

v2: refine amdgpu_rap.h

Signed-off-by: Wenhui Sheng &lt;Wenhui.Sheng@amd.com&gt;
Reviewed-by: Guchun Chen &lt;Guchun.Chen@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable umc 8.7 functions in gmc v10</title>
<updated>2020-07-30T19:36:33Z</updated>
<author>
<name>John Clements</name>
<email>john.clements@amd.com</email>
</author>
<published>2020-07-28T06:22:54Z</published>
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<id>urn:sha1:01eee24fceb9a64b2dc3b3ccb7b7c6852aa7a403</id>
<content type='text'>
add support for umc 8.7 initialization

add umc 8.7 source to makefile

Reviewed-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Signed-off-by: John Clements &lt;john.clements@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm amdgpu: SI UVD add uvd_v3_1 to makefile</title>
<updated>2020-07-01T05:59:24Z</updated>
<author>
<name>Sonny Jiang</name>
<email>sonny.jiang@amd.com</email>
</author>
<published>2020-06-10T20:19:19Z</published>
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<id>urn:sha1:74df08fddf44a7d1a48eeae1dc0a72c60eb9cc4b</id>
<content type='text'>
Signed-off-by: Sonny Jiang &lt;sonny.jiang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Support Sienna_Cichlid KFD v4</title>
<updated>2020-07-01T05:59:11Z</updated>
<author>
<name>Yong Zhao</name>
<email>Yong.Zhao@amd.com</email>
</author>
<published>2019-10-01T21:42:20Z</published>
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<id>urn:sha1:3a2f0c813b42996a8fdb14da2cd828156a6fdd12</id>
<content type='text'>
v4: drop get_tile_config, comment out other callbacks

Signed-off-by: Yong Zhao &lt;Yong.Zhao@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add JPEG3.0 support for Sienna_Cichlid</title>
<updated>2020-07-01T05:59:09Z</updated>
<author>
<name>Leo Liu</name>
<email>leo.liu@amd.com</email>
</author>
<published>2019-11-15T18:23:10Z</published>
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<id>urn:sha1:dfd57dbf44ddc70c90c76f83b2deb46e5dd40ce3</id>
<content type='text'>
With basic IP block functions and ring functions

Signed-off-by: Leo Liu &lt;leo.liu@amd.com&gt;
Reviewed-by: James Zhu &lt;James.Zhu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add VCN3.0 support for Sienna_Cichlid</title>
<updated>2020-07-01T05:59:09Z</updated>
<author>
<name>Leo Liu</name>
<email>leo.liu@amd.com</email>
</author>
<published>2019-11-15T17:45:55Z</published>
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<id>urn:sha1:cf14826cdfb5c9fe10f98210d040b9d7486c381d</id>
<content type='text'>
With basic IP block functions and ring functions

Signed-off-by: Leo Liu &lt;leo.liu@amd.com&gt;
Reviewed-by: James Zhu &lt;James.Zhu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add support for athub v2.1</title>
<updated>2020-07-01T05:59:07Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2019-09-25T08:44:46Z</published>
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<id>urn:sha1:45d76eebd874511f9579dd8917b9385d3f9fa137</id>
<content type='text'>
Add athub v2.1 function and support to compile it.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add sdma ip block for sienna_cichlid (v5)</title>
<updated>2020-06-03T17:52:04Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2019-06-17T05:38:29Z</published>
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<id>urn:sha1:157e72e831cb8f323108b5df6d0b148aef9507fb</id>
<content type='text'>
Sienna_Cichlid have 4 sdma controllers.

v2: add missing license to sdma_common.h (Alex)
v3: rebase (Alex)
v4: squash in policy fix (Alex)
v4: squash in fw_name fix

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add support gfxhub for sienna_cichlid (v3)</title>
<updated>2020-06-03T17:52:01Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2019-06-16T14:27:00Z</published>
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<id>urn:sha1:af01d47d3c22cb1b1f7f74e22595beeed956c9b5</id>
<content type='text'>
GFX10.3 is used for sienna_cichlid.

v2: squash in BANK_SELECT and FRAGMENT_SIZE fixes (Alex)
v3: squash in smallk update (Alex)

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
