linux/drivers/gpu/drm/amd/amdgpu/Makefile, branch v5.4

drm/amdgpu: make pmu support optional, again

2019-10-02T17:58:33Z

When CONFIG_PERF_EVENTS is disabled, we cannot compile the pmu portion of the amdgpu driver: drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:48:38: error: no member named 'hw' in 'struct perf_event' struct hw_perf_event *hwc = &event->hw; ~~~~~ ^ drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:51:13: error: no member named 'attr' in 'struct perf_event' if (event->attr.type != event->pmu->type) ~~~~~ ^ ... The same bug was already fixed by commit d155bef0636e ("amdgpu: make pmu support optional") but broken again by what looks like an incorrectly rebased patch. Fixes: 64f55e629237 ("drm/amdgpu: Add RAS EEPROM table.") Signed-off-by: Arnd Bergmann Signed-off-by: Alex Deucher

drm/amdgpu: Vega20 SMU I2C HW engine controller.

2019-08-27T14:17:35Z

Implement HW I2C enigne controller to be used by the RAS EEPROM table manager. This is based on code from ATITOOLs. v2: Rename the file and all function prefixes to smu_v11_0_i2c By Luben's observation always fill the TX fifo to full so we don't have garbadge interpreted by the slave as valid data. v3: Remove preemption disable as the HW I2C controller will not stop the clock on empty TX fifo and so it's not critical to keep not empty queue. Switch to fast mode 400 khz SCL clock for faster read and write. v5: Restore clock gating before releasing I2C bus and fix some style comments. v6: squash in warning fix, fix includes (Alex) Signed-off-by: Andrey Grodzovsky Reviewed-by: Luben Tuikov Signed-off-by: Alex Deucher

drm/amdgpu: Add RAS EEPROM table.

2019-08-27T13:17:14Z

Add RAS EEPROM table manager to eanble RAS errors to be stored upon appearance and retrived on driver load. v2: Fix some prints. v3: Fix checksum calculation. Make table record and header structs packed to do correct byte value sum. Fix record crossing EEPROM page boundry. v4: Fix byte sum val calculation for record - look at sizeof(record). Fix some style comments. v5: Add description to EEPROM_TABLE_RECORD_SIZE and syntax fixes. Signed-off-by: Andrey Grodzovsky Reviewed-by: Luben Tuikov Signed-off-by: Alex Deucher

drm/amdgpu: add psp_v12_0 for renoir (v2)

2019-08-12T17:47:50Z

1. Add psp ip block 2. Use direct loading type by default and it can also config psp loading type. 3. Bypass sos fw loading and xgmi&ras interface v2: drop TA loading Acked-by: Huang Rui Signed-off-by: Aaron Liu Reviewed-by: Huang Rui Signed-off-by: Alex Deucher

drm/amdgpu: split athub clock gating from mmhub

2019-08-12T17:47:48Z

Untie the bind of get/set athub CG state from mmhub, for cosmetic fix and Asic not using mmhub 1.0. Besides, also fix wrong athub CG state in amdgpu_pm_info. Signed-off-by: Le Ma Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher

drm/amdgpu: initialize reg base for navi12

2019-08-02T15:30:39Z

Set up the register offset map for navi12. Signed-off-by: Xiaojie Yuan Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: add umc v6_1 query error count support

2019-07-31T19:49:16Z

Implement umc query_ras_error_count function to support querry both correctable and uncorrectable error Signed-off-by: Hawking Zhang Signed-off-by: Tao Zhou Reviewed-by: Dennis Li Signed-off-by: Alex Deucher

drm/amdgpu: add VCN2.5 basic supports

2019-07-18T19:18:04Z

i.e. basic VCN IP SW structures VCN is the video codec block on the GPU. Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdkfd: Implement kfd2kgd_calls for Arcturus

2019-07-18T19:18:04Z

Arcturus shares most of the kfd2kgd_calls with gfx9. But due to SDMA register address change, it can't share SDMA related functions. Export gfx9 kfd2kgd_calls and implement SDMA related functions for Arcturus. Signed-off-by: Oak Zeng Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdgpu: dynamically initialize IP offset for Arcturus

2019-07-18T19:18:02Z

Add support for the IP offsets on Arcturus. Signed-off-by: Le Ma Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher