<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/Makefile, branch v6.3</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.3</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.3'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2023-02-14T20:47:15Z</updated>
<entry>
<title>drm/amd/amdgpu: implement mode2 reset on smu_v13_0_10</title>
<updated>2023-02-14T20:47:15Z</updated>
<author>
<name>Kenneth Feng</name>
<email>kenneth.feng@amd.com</email>
</author>
<published>2023-02-10T05:04:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=230dd6bb61173acccdfbf855ba907286e850cd67'/>
<id>urn:sha1:230dd6bb61173acccdfbf855ba907286e850cd67</id>
<content type='text'>
implement mode2 reset on smu_v13_0_10

Signed-off-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: add complete header search path</title>
<updated>2023-02-08T22:35:55Z</updated>
<author>
<name>Randy Dunlap</name>
<email>rdunlap@infradead.org</email>
</author>
<published>2023-02-04T03:27:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=93b1a791c0a09311b61c0f7ed8c5332f7bff3f38'/>
<id>urn:sha1:93b1a791c0a09311b61c0f7ed8c5332f7bff3f38</id>
<content type='text'>
The path for the "mod_info_packet.h" header file is
incomplete, so add its location to the header search path
in the amdgpu Makefile.

See on ARCH=alpha (275 times in one build).

In file included from ../drivers/gpu/drm/amd/amdgpu/amdgpu.h:90,
                 from ../drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:43:
../drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.h:62:10: fatal error: mod_info_packet.h: No such file or directory
   62 | #include "mod_info_packet.h"
      |          ^~~~~~~~~~~~~~~~~~~
compilation terminated.

Fixes: 5b49da02ddbe ("drm/amd/display: Enable Freesync over PCon")
Signed-off-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Cc: Signed-off-by: Sung Joon Kim &lt;sungkim@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: Christian König &lt;christian.koenig@amd.com&gt;
Cc: "Pan, Xinhui" &lt;Xinhui.Pan@amd.com&gt;
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add gfx ras function on gfx v11_0_3</title>
<updated>2023-01-17T21:11:50Z</updated>
<author>
<name>YiPeng Chai</name>
<email>YiPeng.Chai@amd.com</email>
</author>
<published>2022-11-02T06:07:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=89e4c448817835700de108edcb11f26a88414986'/>
<id>urn:sha1:89e4c448817835700de108edcb11f26a88414986</id>
<content type='text'>
Add gfx ras function on gfx v11_0_3.

V2:
 1. Add separate source files for gfx v11_0_3.
 2. Create a common function to initialize gfx ras block.

V3:
 1. Rename amdgpu_gfx_ras_block_init to amdgpu_gfx_ras_sw_init.
 2. Adjust the calling position of amdgpu_gfx_ras_sw_init.
 3. Remove gfx_v11_0_3_ras_ops.

V4:
 Revert changes in amdgpu_ras_interrupt_poison_consumption_handler.

V5:
 1. Remove invalid include file in gfx_v11_0_3.c.
 2. Reduce the number of parameters of amdgpu_gfx_ras_sw_init.

Signed-off-by: YiPeng Chai &lt;YiPeng.Chai@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add poison mode query for df v4_3</title>
<updated>2022-12-15T17:19:30Z</updated>
<author>
<name>Candice Li</name>
<email>candice.li@amd.com</email>
</author>
<published>2022-09-19T06:47:56Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e4f665de417d8b923e638da1751c2c94eb68c713'/>
<id>urn:sha1:e4f665de417d8b923e638da1751c2c94eb68c713</id>
<content type='text'>
Add poison mode query support on df v4_3.

Signed-off-by: Candice Li &lt;candice.li@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Introduce gfx software ring (v9)</title>
<updated>2022-12-02T15:04:27Z</updated>
<author>
<name>Jiadong.Zhu</name>
<email>Jiadong.Zhu@amd.com</email>
</author>
<published>2022-09-07T01:40:47Z</published>
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<id>urn:sha1:ded946f3f6399003ea0bdcc8911bc2fc3a7313c6</id>
<content type='text'>
The software ring is created to support priority context while there is only
one hardware queue for gfx.

Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the ring muxer. The
packages committed on the software ring are copied to the real ring.

v2: Use array to store software ring entry.
v3: Remove unnecessary prints.
v4: Remove amdgpu_ring_sw_init/fini functions,
using gtt for sw ring buffer for later dma copy
optimization.
v5: Allocate ring entry dynamically in the muxer.
v6: Update comments for the ring muxer.
v7: Modify for function naming.
v8: Combine software ring functions into amdgpu_ring_mux.c
v9: Use kernel-doc comment on the get_rptr function.

Cc: Christian Koenig &lt;Christian.Koenig@amd.com&gt;
Cc: Luben Tuikov &lt;Luben.Tuikov@amd.com&gt;
Cc: Andrey Grodzovsky  &lt;Andrey.Grodzovsky@amd.com&gt;
Cc: Michel Dänzer &lt;michel@daenzer.net&gt;
Signed-off-by: Jiadong.Zhu &lt;Jiadong.Zhu@amd.com&gt;
Acked-by: Huang Rui &lt;ray.huang@amd.com&gt;
Acked-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: rename the files for HMM handling</title>
<updated>2022-11-17T05:23:36Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2022-11-09T11:28:46Z</published>
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<id>urn:sha1:d9483ecd327b7537c6a51cab515b5faad21b8200</id>
<content type='text'>
Clean that up a bit, no functional change.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable imu_rlc_ram programming for v11_0_3</title>
<updated>2022-08-30T20:37:14Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2022-07-02T02:20:03Z</published>
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<id>urn:sha1:f926464e59b7029b02d731a9f8a31419ff973ed3</id>
<content type='text'>
All gc v11_0_3 registers in gcvml2 range have different
register offset from the ones in gc v11_0_0. v11_0_3
imu_rlc_ram programming has to be separated from v11_0_0
implementation

v2: fix checkpatch errors (Alex)

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Yang Wang &lt;KevinYang.Wang@amd.com&gt;
Reviewed-by: Frank Min &lt;Frank.Min@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add gfxhub_v3_0_3 support</title>
<updated>2022-08-30T20:36:54Z</updated>
<author>
<name>Yang Wang</name>
<email>KevinYang.Wang@amd.com</email>
</author>
<published>2022-07-01T09:19:27Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9436ac31c73526b1e070c050ee83c3870125bf82'/>
<id>urn:sha1:9436ac31c73526b1e070c050ee83c3870125bf82</id>
<content type='text'>
add gfxhub_v3_0_3 support

Signed-off-by: Yang Wang &lt;KevinYang.Wang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add mode2 reset for sienna_cichlid</title>
<updated>2022-08-16T22:14:31Z</updated>
<author>
<name>Victor Zhao</name>
<email>Victor.Zhao@amd.com</email>
</author>
<published>2022-07-28T02:44:47Z</published>
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<id>urn:sha1:672c0218e3e22ccaeb2911da8d3b784d3b6cc1d8</id>
<content type='text'>
To meet the requirement for multi container usecase which needs
a quicker reset and not causing VRAM lost, adding the Mode2
reset handler for sienna_cichlid.

v2: move skip mode2 flag part separately

v3: remove the use of asic_reset_res

Signed-off-by: Victor Zhao &lt;Victor.Zhao@amd.com&gt;
Acked-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable support for psp 13.0.4 block</title>
<updated>2022-07-29T19:24:38Z</updated>
<author>
<name>Xiaojian Du</name>
<email>Xiaojian.Du@amd.com</email>
</author>
<published>2022-07-27T07:52:33Z</published>
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<id>urn:sha1:7e8a3ca972adfc89609718c931577a86c494967b</id>
<content type='text'>
This patch will enable support for psp 13.0.4 blcok.

Signed-off-by: Xiaojian Du &lt;Xiaojian.Du@amd.com&gt;
Reviewed-by: Tim Huang &lt;Tim.Huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
