linux/drivers/gpu/drm/amd/amdgpu/amdgpu.h, branch v4.15

drm/amdgpu: Use unsigned ring indices in amdgpu_queue_mgr_map

2017-11-28T22:44:14Z

This matches the corresponding UAPI fields. Treating the ring index as signed could result in accessing random unrelated memory if the MSB was set. Fixes: effd924d2f3b ("drm/amdgpu: untie user ring ids from kernel ring ids v6") Cc: stable@vger.kernel.org Reviewed-by: Alex Deucher Reviewed-by: Christian König Signed-off-by: Michel Dänzer Signed-off-by: Alex Deucher

drm/amdgpu: move UVD/VCE and VCN structure out from union

2017-11-28T22:44:11Z

With the enablement of VCN Dec and Enc from user space, User space queries kernel for the IP information, if HW has UVD/VCE, the info comes from these IP blocks, but this could end up mis-interpret for VCN when they are in the union, the other way same when HW with VCN block. Signed-off-by: Leo Liu Acked-by: Alex Deucher Reviewed-by: Christian König Signed-off-by: Alex Deucher Fixes: 95d0906f8506 ("drm/amdgpu: add initial vcn support and decode tests") Cc: stable@vger.kernel.org Reviewed-and-Tested-by: Michel Dänzer

Merge tag 'drm-for-v4.15-amd-dc' of git://people.freedesktop.org/~airlied/linux

2017-11-17T22:34:42Z

Pull amdgpu DC display code for Vega from Dave Airlie: "This is the pull request for the AMD DC (display code) layer which is a requirement to program the display engines on the new Vega and Raven based GPUs. It also contains support for all amdgpu supported GPUs (CIK, VI, Polaris), which has to be enabled. It is also a kms atomic modesetting compatible driver (unlike the current in-tree display code). I've kept it separate from drm-next because it may have some things that cause you to reject it. Background story: AMD have an internal team creating a shared OS codebase for display at hw bring up time using information from their hardware teams. This process doesn't lead to the most Linux friendly/looking code but we have worked together on cleaning a lot of it up and dealing with sparse/smatch/checkpatch, and having their team internally adhere to Linux coding standards. This tree is a complete history rebased since they started opening it, we decided not to squash it down as the history may have some value. Some of the commits therefore might not reach kernel standards, and we are steadily training people in AMD to better write commit msgs. There is a major bunch of generated bandwidth calculation and verification code that comes from their hardware team. On Vega and before this is float calculations, on Raven (DCN10) this is double based. They do the required things to do FP in the kernel, and I could understand this might raise some issues. Rewriting the bandwidth would be a major undertaken in reverification, it's non-trivial to work out if a display can handle the complete set of mode information thrown at it. Future story: There is a TODO list with this, and it address most of the remaining things that would be nice to refine/remove. The DCN10 code is still under development internally and they push out a lot of patches quite regularly and are supporting this code base with their display team. I think we've reached the point where keeping it out of tree is going to motivate distributions to start carrying the code, so I'd prefer we get it in tree. I think this code is slightly better than STAGING quality but not massively so, I'd really like to see that float/double magic gone and fixed point used, but AMD don't seem to think the accuracy and revalidation of the code is worth the effort" * tag 'drm-for-v4.15-amd-dc' of git://people.freedesktop.org/~airlied/linux: (1110 commits) drm/amd/display: fix MST link training fail division by 0 drm/amd/display: Fix formatting for null pointer dereference fix drm/amd/display: Remove dangling planes on dc commit state drm/amd/display: add flip_immediate to commit update for stream drm/amd/display: Miss register MST encoder cbs drm/amd/display: Fix warnings on S3 resume drm/amd/display: use num_timing_generator instead of pipe_count drm/amd/display: use configurable FBC option in dm drm/amd/display: fix AZ clock not enabled before program AZ endpoint amdgpu/dm: Don't use DRM_ERROR in amdgpu_dm_atomic_check amd/display: Fix potential null dereference in dce_calcs.c amdgpu/dm: Remove unused forward declaration drm/amdgpu: Remove unused dc_stream from amdgpu_crtc amdgpu/dc: Fix double unlock in amdgpu_dm_commit_planes amdgpu/dc: Fix missing null checks in amdgpu_dm.c amdgpu/dc: Fix potential null dereferences in amdgpu_dm.c amdgpu/dc: fix more indentation warnings amdgpu/dc: handle allocation failures in dc_commit_planes_to_stream. amdgpu/dc: fix indentation warning from smatch. amdgpu/dc: fix non-ansi function decls. ...

drm/amdgpu: busywait KIQ register accessing (v4)

2017-10-19T19:27:19Z

Register accessing is performed when IRQ is disabled. Never sleep in this function. Known issue: dead sleep in many use cases of index/data registers. v2: - wrap polling fence functions. - don't trigger IRQ for polling in case of wrongly fence signal. v3: - handle wrap round gracefully. - add comments for polling function v4: - don't return negative timeout confused with error code Signed-off-by: pding Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu:reduce wb to 512 slot

2017-10-19T19:27:16Z

with current WB usage we only use 57 slots, so 512 is extreamly sufficient, and reduce to 512 can make WB fit into one page. Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: move the VRAM lost counter per context

2017-10-19T19:27:04Z

Instead of per device track the VRAM lost per context and return ECANCELED instead of ENODEV. Signed-off-by: Christian König Reviewed-by: Nicolai Hähnle Signed-off-by: Alex Deucher

drm/amdgpu: keep copy of VRAM lost counter in job

2017-10-19T19:27:03Z

Instead of reading the current counter from fpriv. Signed-off-by: Christian König Reviewed-by: Nicolai Hähnle Signed-off-by: Alex Deucher

drm/amdgpu: Move old fence waiting before reservation lock is aquired v2

2017-10-19T19:26:59Z

Helps avoiding deadlock during GPU reset. Added mutex to amdgpu_ctx to preserve order of fences on a ring. v2: Put waiting logic in a function in a seperate function in amdgpu_ctx.c Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: add plumbing for ctx priority changes v2

2017-10-09T20:30:24Z

Introduce amdgpu_ctx_priority_override(). A mechanism to override a context's priority. An override can be terminated by setting the override to AMD_SCHED_PRIORITY_UNSET. v2: change refcounted interface for a direct set Signed-off-by: Andres Rodriguez Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: implement ring set_priority for gfx_v8 compute v9

2017-10-09T20:30:21Z

Programming CP_HQD_QUEUE_PRIORITY enables a queue to take priority over other queues on the same pipe. Multiple queues on a pipe are timesliced so this gives us full precedence over other queues. Programming CP_HQD_PIPE_PRIORITY changes the SPI_ARB_PRIORITY of the wave as follows: 0x2: CS_H 0x1: CS_M 0x0: CS_L The SPI block will then dispatch work according to the policy set by SPI_ARB_PRIORITY. In the current policy CS_H is higher priority than gfx. In order to prevent getting stuck in loops of resources bouncing between GFX and high priority compute and introducing further latency, we statically reserve a portion of the pipe. v2: fix srbm_select to ring->queue and use ring->funcs->type v3: use AMD_SCHED_PRIORITY_* instead of AMDGPU_CTX_PRIORITY_* v4: switch int to enum amd_sched_priority v5: corresponding changes for srbm_lock v6: change CU reservation to PIPE_PERCENT allocation v7: use kiq instead of MMIO v8: back to MMIO, and make the implementation sleep safe. v9: corresponding changes for splitting HIGH into _HW/_SW Acked-by: Christian König Signed-off-by: Andres Rodriguez Signed-off-by: Alex Deucher