linux/drivers/gpu/drm/amd/amdgpu/amdgpu.h, branch v4.7

Revert "drm/amdgpu: add pipeline sync while vmid switch in same ctx"

2016-06-13T22:59:17Z

This reverts commit 2ba272d7bde27e1db2cf1c6cee49b01b7ea08989. The issue fixed by this patch is specific to compute rings and the previous patch was enough. Additionally, this patch as been traced to strange behavior on some CZ systems so we might as well drop it.

amdgpu: fix asic initialization for virtualized environments (v2)

2016-06-13T19:25:20Z

When executing in a PCI passthrough based virtuzliation environemnt, the hypervisor will usually attempt to send a PCIe bus reset signal to the ASIC when the VM reboots. In this scenario, the card is not correctly initialized, but we still consider it to be posted. Therefore, in a passthrough based environemnt we should always post the card to guarantee it is in a good state for driver initialization. However, if we are operating in SR-IOV mode it is up to the GIM driver to manage the asic state, therefore we should not post the card (and shouldn't be able to do it either). v2: add missing semi-colon Reviewed-by: Christian König Signed-off-by: Andres Rodriguez Signed-off-by: Alex Deucher

drm/amdgpu: add pipeline sync while vmid switch in same ctx

2016-06-09T14:49:01Z

Since vmid-mgr supports vmid sharing in one vm, the same ctx could get different vmids for two emits without vm flush, vm_flush could be done in another ring. Signed-off-by: Chunming Zhou Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: create fence slab once when amdgpu module init.

2016-05-13T18:30:22Z

This avoids problems with multiple GPUs. For example, if the first GPU failed before amdgpu_fence_init() was called, amdgpu_fence_slab_ref is still 0 and it will get decremented in amdgpu_fence_driver_fini(). This will lead to a crash during init of the second GPU since amdgpu_fence_slab_ref is not 0. v2: add functions for init/exit instead of moving the variables into the driver. Signed-off-by: Rex Zhu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: fix and cleanup user fence handling v2

2016-05-11T17:30:32Z

We leaked the BO in the error pass, additional to that we only have one user fence for all IBs in a job. v2: remove white space changes Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: move VM fields into job

2016-05-11T17:30:31Z

They are the same for all IBs. Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: move the context from the IBs into the job

2016-05-11T17:30:31Z

We only have one context for all IBs. Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: move context switch handling into common code v2

2016-05-11T17:30:30Z

It was a source of bugs to repeat that in each IP version. v2: rename parameter Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: use fence_context to judge ctx switch v2

2016-05-11T16:31:27Z

Use of the ctx pointer is not safe, because they are likely already be assigned to another ctx when doing comparing. v2: recreate from scratch, avoid all unnecessary changes. Signed-off-by: Christian König Reviewed-by: Monk.Liu Signed-off-by: Alex Deucher

drm/amdgpu: Support DRM_MODE_PAGE_FLIP_ASYNC (v2)

2016-05-11T16:31:25Z

When this flag is set, we program the hardware to execute the flip during horizontal blank (i.e. for the next scanline) instead of during vertical blank (i.e. for the next frame). Ported from radeon commit: drm/radeon: Support DRM_MODE_PAGE_FLIP_ASYNC v2: drop DAL change for upstream Reviewed-by: Michel Dänzer Signed-off-by: Alex Deucher