<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu.h, branch v5.1</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.1</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.1'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-02-15T16:15:37Z</updated>
<entry>
<title>drm/amdgpu: Check if fd really is an amdgpu fd.</title>
<updated>2019-02-15T16:15:37Z</updated>
<author>
<name>Bas Nieuwenhuizen</name>
<email>bas@basnieuwenhuizen.nl</email>
</author>
<published>2019-01-30T01:53:21Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=021830d24ba55a578f602979274965344c8e6284'/>
<id>urn:sha1:021830d24ba55a578f602979274965344c8e6284</id>
<content type='text'>
Otherwise we interpret the file private data as drm &amp; amdgpu data
while it might not be, possibly allowing one to get memory corruption.

Signed-off-by: Bas Nieuwenhuizen &lt;bas@basnieuwenhuizen.nl&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix sdma doorbell range setting</title>
<updated>2019-01-25T21:15:34Z</updated>
<author>
<name>Oak Zeng</name>
<email>Oak.Zeng@amd.com</email>
</author>
<published>2018-12-18T02:03:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8987e2e256be3551436a5abc3c48d0eb4d81084e'/>
<id>urn:sha1:8987e2e256be3551436a5abc3c48d0eb4d81084e</id>
<content type='text'>
Different ASIC has different SDMA queue number so
different SDMA doorbell range. Introduce an extra
parameter to sdma_doorbell_range function and set
sdma doorbell range correctly.

Signed-off-by: Oak Zeng &lt;Oak.Zeng@amd.com&gt;
Reviewed-by: Philip Yang &lt;Philip.Yang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add need_reset_on_init asic callback (v2)</title>
<updated>2019-01-14T20:04:55Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-11-01T04:54:27Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=444018893abfde1df86be9d4be3e0c84832397dd'/>
<id>urn:sha1:444018893abfde1df86be9d4be3e0c84832397dd</id>
<content type='text'>
Used to determine if we need to reset the asic on init due
to the driver having been previously loaded or not shutdown
cleanly.  E.g., kexec or VM passthrough.

v2: rebase

Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add sysfs file for PCIe usage v5</title>
<updated>2019-01-14T20:04:54Z</updated>
<author>
<name>Kent Russell</name>
<email>kent.russell@amd.com</email>
</author>
<published>2019-01-03T13:12:39Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b45e18acd394954c24943762ada5d8dada75f2b9'/>
<id>urn:sha1:b45e18acd394954c24943762ada5d8dada75f2b9</id>
<content type='text'>
Add a sysfs file that reports the number of bytes transmitted and
received in the last second. This can be used to approximate the PCIe
bandwidth usage over the last second.

v2: Clarify use of mps as estimation of bandwidth
v3: Don't make the file on APUs
v4: Early exit for APUs in the read function, change output to
    display "packets-received packets-sent mps"
v5: fix missing header for si (Alex)

Signed-off-by: Kent Russell &lt;kent.russell@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm</title>
<updated>2018-12-25T19:48:26Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2018-12-25T19:48:26Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4971f090aa7f6ce5daa094ce4334f6618f93a7eb'/>
<id>urn:sha1:4971f090aa7f6ce5daa094ce4334f6618f93a7eb</id>
<content type='text'>
Pull drm updates from Dave Airlie:
 "Core:
   - shared fencing staging removal
   - drop transactional atomic helpers and move helpers to new location
   - DP/MST atomic cleanup
   - Leasing cleanups and drop EXPORT_SYMBOL
   - Convert drivers to atomic helpers and generic fbdev.
   - removed deprecated obj_ref/unref in favour of get/put
   - Improve dumb callback documentation
   - MODESET_LOCK_BEGIN/END helpers

  panels:
   - CDTech panels, Banana Pi Panel, DLC1010GIG,
   - Olimex LCD-O-LinuXino, Samsung S6D16D0, Truly NT35597 WQXGA,
   - Himax HX8357D, simulated RTSM AEMv8.
   - GPD Win2 panel
   - AUO G101EVN010

  vgem:
   - render node support

  ttm:
   - move global init out of drivers
   - fix LRU handling for ghost objects
   - Support for simultaneous submissions to multiple engines

  scheduler:
   - timeout/fault handling changes to help GPU recovery
   - helpers for hw with preemption support

  i915:
   - Scaler/Watermark fixes
   - DP MST + powerwell fixes
   - PSR fixes
   - Break long get/put shmemfs pages
   - Icelake fixes
   - Icelake DSI video mode enablement
   - Engine workaround improvements

  amdgpu:
   - freesync support
   - GPU reset enabled on CI, VI, SOC15 dGPUs
   - ABM support in DC
   - KFD support for vega12/polaris12
   - SDMA paging queue on vega
   - More amdkfd code sharing
   - DCC scanout on GFX9
   - DC kerneldoc
   - Updated SMU firmware for GFX8 chips
   - XGMI PSP + hive reset support
   - GPU reset
   - DC trace support
   - Powerplay updates for newer Polaris
   - Cursor plane update fast path
   - kfd dma-buf support

  virtio-gpu:
   - add EDID support

  vmwgfx:
   - pageflip with damage support

  nouveau:
   - Initial Turing TU104/TU106 modesetting support

  msm:
   - a2xx gpu support for apq8060 and imx5
   - a2xx gpummu support
   - mdp4 display support for apq8060
   - DPU fixes and cleanups
   - enhanced profiling support
   - debug object naming interface
   - get_iova/page pinning decoupling

  tegra:
   - Tegra194 host1x, VIC and display support enabled
   - Audio over HDMI for Tegra186 and Tegra194

  exynos:
   - DMA/IOMMU refactoring
   - plane alpha + blend mode support
   - Color format fixes for mixer driver

  rcar-du:
   - R8A7744 and R8A77470 support
   - R8A77965 LVDS support

  imx:
   - fbdev emulation fix
   - multi-tiled scalling fixes
   - SPDX identifiers

  rockchip
   - dw_hdmi support
   - dw-mipi-dsi + dual dsi support
   - mailbox read size fix

  qxl:
   - fix cursor pinning

  vc4:
   - YUV support (scaling + cursor)

  v3d:
   - enable TFU (Texture Formatting Unit)

  mali-dp:
   - add support for linear tiled formats

  sun4i:
   - Display Engine 3 support
   - H6 DE3 mixer 0 support
   - H6 display engine support
   - dw-hdmi support
   - H6 HDMI phy support
   - implicit fence waiting
   - BGRX8888 support

  meson:
   - Overlay plane support
   - implicit fence waiting
   - HDMI 1.4 4k modes

  bridge:
   - i2c fixes for sii902x"

* tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm: (1403 commits)
  drm/amd/display: Add fast path for cursor plane updates
  drm/amdgpu: Enable GPU recovery by default for CI
  drm/amd/display: Fix duplicating scaling/underscan connector state
  drm/amd/display: Fix unintialized max_bpc state values
  Revert "drm/amd/display: Set RMX_ASPECT as default"
  drm/amdgpu: Fix stub function name
  drm/msm/dpu: Fix clock issue after bind failure
  drm/msm/dpu: Clean up dpu_media_info.h static inline functions
  drm/msm/dpu: Further cleanups for static inline functions
  drm/msm/dpu: Cleanup the debugfs functions
  drm/msm/dpu: Remove dpu_irq and unused functions
  drm/msm: Make irq_postinstall optional
  drm/msm/dpu: Cleanup callers of dpu_hw_blk_init
  drm/msm/dpu: Remove unused functions
  drm/msm/dpu: Remove dpu_crtc_is_enabled()
  drm/msm/dpu: Remove dpu_crtc_get_mixer_height
  drm/msm/dpu: Remove dpu_dbg
  drm/msm: dpu: Remove crtc_lock
  drm/msm: dpu: Remove vblank_requested flag from dpu_crtc
  drm/msm: dpu: Separate crtc assignment from vblank enable
  ...
</content>
</entry>
<entry>
<title>drm/amdgpu: Limit vm max ctx number to 4096</title>
<updated>2018-12-10T20:21:13Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2018-10-24T08:10:33Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=08d1bdd4cc57e89d037205687a61d2b6ff9dddd4'/>
<id>urn:sha1:08d1bdd4cc57e89d037205687a61d2b6ff9dddd4</id>
<content type='text'>
driver need to reserve resource for each ctx for
some hw features. so add this limitation.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add KFD VRAM limit checking</title>
<updated>2018-12-07T23:13:15Z</updated>
<author>
<name>Felix Kuehling</name>
<email>Felix.Kuehling@amd.com</email>
</author>
<published>2018-11-20T01:05:54Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=611736d8447c0c48a172db0b968dddae60696a72'/>
<id>urn:sha1:611736d8447c0c48a172db0b968dddae60696a72</id>
<content type='text'>
We don't want KFD processes evicting each other over VRAM usage.
Therefore prevent overcommitting VRAM among KFD applications with
a per-GPU limit. Also leave enough room for page tables on top
of the application memory usage.

Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Reviewed-by: Eric Huang &lt;JinHuiEric.Huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enlarge maximum waiting time of KIQ</title>
<updated>2018-12-04T20:01:20Z</updated>
<author>
<name>wentalou</name>
<email>wentalou@amd.com</email>
</author>
<published>2018-12-03T02:49:50Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4944af670bc2c7da77ac17b295656d913e3898f4'/>
<id>urn:sha1:4944af670bc2c7da77ac17b295656d913e3898f4</id>
<content type='text'>
KIQ in VF’s init delayed by another VF’s reset,
which would cause late_init failed occasionally.
MAX_KIQ_REG_TRY enlarged from 20 to 80 would fix this issue.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Wentao Lou &lt;Wentao.Lou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Implement concurrent asic reset for XGMI.</title>
<updated>2018-12-03T16:15:14Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2018-11-29T20:14:27Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d4535e2c018bba71b49edeb5e396183920f5d341'/>
<id>urn:sha1:d4535e2c018bba71b49edeb5e396183920f5d341</id>
<content type='text'>
Use per hive wq to concurrently send reset commands to all nodes
in the hive.

v2:
Switch to system_highpri_wq after dropping dedicated queue.
Fix non XGMI code path KASAN error.
Stop  the hive reset for each node loop if there
is a reset failure on any of the nodes.

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Refactor GPU reset for XGMI hive case</title>
<updated>2018-11-28T20:55:36Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2018-11-22T23:57:08Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=26bc534094ed45fdedef6b4ce8b96030340c5ce7'/>
<id>urn:sha1:26bc534094ed45fdedef6b4ce8b96030340c5ce7</id>
<content type='text'>
For XGMI hive case do reset in steps where each step iterates over
all devs in hive. This especially important for asic reset
since all PSP FW in hive must come up within a limited time
(around 1 sec) to properply negotiate the link.
Do this by  refactoring  amdgpu_device_gpu_recover and amdgpu_device_reset
into pre_asic_reset, asic_reset and post_asic_reset functions where is part
is exectued for all the GPUs in the hive before going to the next step.

v2: Update names for amdgpu_device_lock/unlock functions.

v3: Introduce per hive locking to avoid multiple resets for GPUs
    in same hive.
v4:
Remove delayed_workqueue()/ttm_bo_unlock_delayed_workqueue() - they
are copy &amp; pasted over from radeon and on amdgpu there isn't
any reason for that any more.

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
