<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu.h, branch v5.15</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.15</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.15'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2021-10-05T17:02:31Z</updated>
<entry>
<title>drm/amdgpu: handle the case of pci_channel_io_frozen only in amdgpu_pci_resume</title>
<updated>2021-10-05T17:02:31Z</updated>
<author>
<name>Guchun Chen</name>
<email>guchun.chen@amd.com</email>
</author>
<published>2021-10-01T01:48:50Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=248b061689a40f4fed05252ee2c89f87cf26d7d8'/>
<id>urn:sha1:248b061689a40f4fed05252ee2c89f87cf26d7d8</id>
<content type='text'>
In current code, when a PCI error state pci_channel_io_normal is detectd,
it will report PCI_ERS_RESULT_CAN_RECOVER status to PCI driver, and PCI
driver will continue the execution of PCI resume callback report_resume by
pci_walk_bridge, and the callback will go into amdgpu_pci_resume
finally, where write lock is releasd unconditionally without acquiring
such lock first. In this case, a deadlock will happen when other threads
start to acquire the read lock.

To fix this, add a member in amdgpu_device strucutre to cache
pci_channel_state, and only continue the execution in amdgpu_pci_resume
when it's pci_channel_io_frozen.

Fixes: c9a6b82f45e2 ("drm/amdgpu: Implement DPC recovery")
Suggested-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Signed-off-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Reviewed-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Increase HWIP_MAX_INSTANCE to 10</title>
<updated>2021-09-14T20:14:41Z</updated>
<author>
<name>Ernst Sjöstrand</name>
<email>ernstp@gmail.com</email>
</author>
<published>2021-09-02T07:50:27Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=67a44e659888569a133a8f858c8230e9d7aad1d5'/>
<id>urn:sha1:67a44e659888569a133a8f858c8230e9d7aad1d5</id>
<content type='text'>
Seems like newer cards can have even more instances now.
Found by UBSAN: array-index-out-of-bounds in
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:318:29
index 8 is out of range for type 'uint32_t *[8]'

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1697
Cc: stable@vger.kernel.org
Signed-off-by: Ernst Sjöstrand &lt;ernstp@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add driver infrastructure for MCA RAS</title>
<updated>2021-08-24T19:36:18Z</updated>
<author>
<name>John Clements</name>
<email>john.clements@amd.com</email>
</author>
<published>2021-08-24T05:24:25Z</published>
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<id>urn:sha1:3907c492184e13a5d8d336963a6ec1f6ebe0064d</id>
<content type='text'>
Add MCA specific IP blocks targetting RAS features

Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: John Clements &lt;john.clements@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: drop the unnecessary intermediate percent-based transition</title>
<updated>2021-08-16T19:35:56Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2021-02-10T02:16:08Z</published>
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<id>urn:sha1:0d8318e11203c2d1ec54ae9a4aad71fb0ecf9c36</id>
<content type='text'>
Currently, the readout of fan speed pwm is transited into percent-based
and then pwm-based. However, the transition into percent-based is totally
unnecessary and make the final output less accurate.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: create amdgpu_vkms (v4)</title>
<updated>2021-08-06T01:17:58Z</updated>
<author>
<name>Ryan Taylor</name>
<email>Ryan.Taylor@amd.com</email>
</author>
<published>2021-06-07T18:53:06Z</published>
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<id>urn:sha1:84ec374bd580364a32818c9fc269c19d6e931cab</id>
<content type='text'>
Modify the VKMS driver into an api that dce_virtual can use to create
virtual displays that obey drm's atomic modesetting api.

v2: Made local functions static.

v3: Switched vkms_output kzalloc for kcalloc.
    Cleanup patches by moving display mode fixes to this patch.

v4: Update atomic_check and atomic_update to comply with new kms api.

Signed-off-by: Ryan Taylor &lt;Ryan.Taylor@amd.com&gt;
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Suggested-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Rename amdgpu_acpi_is_s0ix_supported</title>
<updated>2021-07-27T16:04:26Z</updated>
<author>
<name>Pratik Vishwakarma</name>
<email>Pratik.Vishwakarma@amd.com</email>
</author>
<published>2021-07-26T08:24:25Z</published>
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<id>urn:sha1:d0260f62eeeb4646af7449006452decfed202fd7</id>
<content type='text'>
Rename amdgpu_acpi_is_s0ix_supported to better explain
functionality by renaming to amdgpu_acpi_is_s0ix_active

Signed-off-by: Pratik Vishwakarma &lt;Pratik.Vishwakarma@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: split amdgpu_device_access_vram() into two small parts</title>
<updated>2021-07-16T17:58:13Z</updated>
<author>
<name>Kevin Wang</name>
<email>kevin1.wang@amd.com</email>
</author>
<published>2021-07-16T17:57:49Z</published>
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<id>urn:sha1:048af66be7b5ffb107f3696a853a4deb9aa6efec</id>
<content type='text'>
split amdgpu_device_access_vram()
1. amdgpu_device_mm_access(): using MM_INDEX/MM_DATA to access vram
2. amdgpu_device_aper_access(): using vram aperature to access vram (option)

Signed-off-by: Kevin Wang &lt;kevin1.wang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>amdgpu/nv.c - Optimize code for video codec support structure</title>
<updated>2021-07-16T17:46:09Z</updated>
<author>
<name>Veerabadhran Gopalakrishnan</name>
<email>veerabadhran.gopalakrishnan@amd.com</email>
</author>
<published>2021-07-13T17:51:43Z</published>
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<id>urn:sha1:9075096b09e5905ccaa7f7be548593a6530e097f</id>
<content type='text'>
Optimized the code for codec info structure initialization

Signed-off-by: Veerabadhran Gopalakrishnan &lt;veerabadhran.gopalakrishnan@amd.com&gt;
Reviewed-by: James Zhu &lt;James.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Don't flush/invalidate HDP for APUs and A+A</title>
<updated>2021-06-04T20:02:38Z</updated>
<author>
<name>Eric Huang</name>
<email>jinhuieric.huang@amd.com</email>
</author>
<published>2021-06-02T19:05:20Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=810085ddb7b76c1cc5059a1feb3b1250eceacf23'/>
<id>urn:sha1:810085ddb7b76c1cc5059a1feb3b1250eceacf23</id>
<content type='text'>
Integrate two generic functions to determine if HDP
flush is needed for all Asics.

Signed-off-by: Eric Huang &lt;jinhuieric.huang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: attr to control SS2.0 bias level (v2)</title>
<updated>2021-06-04T16:40:00Z</updated>
<author>
<name>Sathishkumar S</name>
<email>sathishkumar.sundararaju@amd.com</email>
</author>
<published>2021-05-30T05:17:16Z</published>
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<id>urn:sha1:30d95a37f46d1be90048c565d3ec380ddecb0541</id>
<content type='text'>
add sysfs attr to read/write smartshift bias level.
document smartshift_bias sysfs attr.

V2: add attr to amdgpu_device_attrs and use attr_update (Lijo)

Signed-off-by: Sathishkumar S &lt;sathishkumar.sundararaju@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
