<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu.h, branch v5.8</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.8</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.8'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-05-22T17:41:53Z</updated>
<entry>
<title>drm/amdgpu: add apu flags (v2)</title>
<updated>2020-05-22T17:41:53Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-05-15T18:18:29Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=54f78a7655e20792253fdf6969513c5f9169c897'/>
<id>urn:sha1:54f78a7655e20792253fdf6969513c5f9169c897</id>
<content type='text'>
Add some APU flags to simplify handling of different APU
variants.  It's easier to understand the special cases
if we use names flags rather than checking device ids and
silicon revisions.

v2: rebase on latest code

Acked-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DC Debug mask to disable features for bringup</title>
<updated>2020-05-21T16:37:19Z</updated>
<author>
<name>Harry Wentland</name>
<email>harry.wentland@amd.com</email>
</author>
<published>2020-05-01T18:23:37Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8a791dabea181607f27aacb89c5e75a2eaaf0586'/>
<id>urn:sha1:8a791dabea181607f27aacb89c5e75a2eaaf0586</id>
<content type='text'>
[Why]
At bringup we want to be able to disable various power features.

[How]
These features are already exposed as dc_debug_options and exercised
on other OSes. Create a new dc_debug_mask module parameter and expose
relevant bits, in particular
 * DC_DISABLE_PIPE_SPLIT
 * DC_DISABLE_STUTTER
 * DC_DISABLE_DSC
 * DC_DISABLE_CLOCK_GATING

Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add autodump debugfs node for gpu reset v8</title>
<updated>2020-05-18T15:23:37Z</updated>
<author>
<name>Jiange Zhao</name>
<email>Jiange.Zhao@amd.com</email>
</author>
<published>2020-04-26T09:57:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=728e7e0cd61899208e924472b9e641dbeb0775c4'/>
<id>urn:sha1:728e7e0cd61899208e924472b9e641dbeb0775c4</id>
<content type='text'>
When GPU got timeout, it would notify an interested part
of an opportunity to dump info before actual GPU reset.

A usermode app would open 'autodump' node under debugfs system
and poll() for readable/writable. When a GPU reset is due,
amdgpu would notify usermode app through wait_queue_head and give
it 10 minutes to dump info.

After usermode app has done its work, this 'autodump' node is closed.
On node closure, amdgpu gets to know the dump is done through
the completion that is triggered in release().

There is no write or read callback because necessary info can be
obtained through dmesg and umr. Messages back and forth between
usermode app and amdgpu are unnecessary.

v2: (1) changed 'registered' to 'app_listening'
    (2) add a mutex in open() to prevent race condition

v3 (chk): grab the reset lock to avoid race in autodump_open,
          rename debugfs file to amdgpu_autodump,
          provide autodump_read as well,
          style and code cleanups

v4: add 'bool app_listening' to differentiate situations, so that
    the node can be reopened; also, there is no need to wait for
    completion when no app is waiting for a dump.

v5: change 'bool app_listening' to 'enum amdgpu_autodump_state'
    add 'app_state_mutex' for race conditions:
	(1)Only 1 user can open this file node
	(2)wait_dump() can only take effect after poll() executed.
	(3)eliminated the race condition between release() and
	   wait_dump()

v6: removed 'enum amdgpu_autodump_state' and 'app_state_mutex'
    removed state checking in amdgpu_debugfs_wait_dump
    Improve on top of version 3 so that the node can be reopened.

v7: move reinit_completion into open() so that only one user
    can open it.

v8: remove complete_all() from amdgpu_debugfs_wait_dump().

Signed-off-by: Jiange Zhao &lt;Jiange.Zhao@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable hibernate support on Navi1X</title>
<updated>2020-05-08T18:32:16Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-05-07T10:17:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=85625e64295079525e5f841b576f9ab71d2c6237'/>
<id>urn:sha1:85625e64295079525e5f841b576f9ab71d2c6237</id>
<content type='text'>
BACO is needed to support hibernate on Navi1X.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: re-structue members for ip discovery</title>
<updated>2020-05-01T19:19:07Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2020-03-31T19:20:49Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e0c116c1906618823e6fa823a8a727bcea04ac18'/>
<id>urn:sha1:e0c116c1906618823e6fa823a8a727bcea04ac18</id>
<content type='text'>
This is to prepare for initializing discovery tmr size per
ASIC type

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: cleanup IB pool handling a bit</title>
<updated>2020-04-28T20:20:30Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2020-04-01T09:18:21Z</published>
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<id>urn:sha1:9ecefb19c3a6626c27ea7ee72d431f22462e1d54</id>
<content type='text'>
Fix the coding style, move and rename the definitions to
better match what they are supposed to be doing.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: implement TMZ accessor (v3)</title>
<updated>2020-04-28T20:20:29Z</updated>
<author>
<name>Luben Tuikov</name>
<email>luben.tuikov@amd.com</email>
</author>
<published>2020-03-19T20:47:51Z</published>
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<id>urn:sha1:c6252390fccdd768d1250a45cbd2a7e3610a1283</id>
<content type='text'>
Implement an accessor of adev-&gt;tmz.enabled. Let not
code around access it as "if (adev-&gt;tmz.enabled)"
as the organization may change. Instead...

Recruit "bool amdgpu_is_tmz(adev)" to return
exactly this Boolean value. That is, this function
is now an accessor of an already initialized and
set adev and adev-&gt;tmz.

Add "void amdgpu_gmc_tmz_set(adev)" to check and
set adev-&gt;gmc.tmz_enabled at initialization
time. After which one uses "bool
amdgpu_is_tmz(adev)" to query whether adev
supports TMZ.

Also, remove circular header file include.

v2: Remove amdgpu_tmz.[ch] as requested.
v3: Move TMZ into GMC.

Signed-off-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add amdgpu_tmz data structure</title>
<updated>2020-04-28T20:20:28Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2020-01-14T15:10:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ae60305ac04ff7bb804fb17962140839daa628c2'/>
<id>urn:sha1:ae60305ac04ff7bb804fb17962140839daa628c2</id>
<content type='text'>
This patch to add amdgpu_tmz structure which stores all tmz related fields.

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add tmz feature parameter (v2)</title>
<updated>2020-04-28T20:20:28Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2019-08-04T08:33:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d7ccb38df5f7ee24e667a4c61b2ce3ff77a7fd6e'/>
<id>urn:sha1:d7ccb38df5f7ee24e667a4c61b2ce3ff77a7fd6e</id>
<content type='text'>
This patch adds tmz parameter to enable/disable
the feature in the amdgpu kernel module. Nomally,
by default, it should be auto (rely on the
hardware capability).

But right now, it need to set "off" to avoid
breaking other developers' work because it's not
totally completed.

Will set "auto" till the feature is stable and
completely verified.

v2: add "auto" option for future use.

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: request reg_val_offs each kiq read reg</title>
<updated>2020-04-23T19:06:41Z</updated>
<author>
<name>Yintian Tao</name>
<email>yttao@amd.com</email>
</author>
<published>2020-04-22T11:58:22Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5420819401cc7048a373d99407a8bb2cca7861c9'/>
<id>urn:sha1:5420819401cc7048a373d99407a8bb2cca7861c9</id>
<content type='text'>
According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 through KIQ
4. client-B poll the seqno-1
5. the kiq complete these two read operation
6. client-A to read the register at the wb buffer and
   get REG-1 value

Therefore, use amdgpu_device_wb_get() to request reg_val_offs
for each kiq read register.

v2: fix the error remove
v3: fix the print typo
v4: remove unused variables

Signed-off-by: Yintian Tao &lt;yttao@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
