<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/amdgpu.h, branch v6.0</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.0</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.0'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2022-08-16T22:08:01Z</updated>
<entry>
<title>drm/amdgpu: Increase tlb flush timeout for sriov</title>
<updated>2022-08-16T22:08:01Z</updated>
<author>
<name>Dusica Milinkovic</name>
<email>Dusica.Milinkovic@amd.com</email>
</author>
<published>2022-08-10T07:43:15Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=373008bfc9cdb0f050258947fa5a095f0657e1bc'/>
<id>urn:sha1:373008bfc9cdb0f050258947fa5a095f0657e1bc</id>
<content type='text'>
[Why]
During multi-vf executing benchmark (Luxmark) observed kiq error timeout.
It happenes because all of VFs do the tlb invalidation at the same time.
Although each VF has the invalidate register set, from hardware side
the invalidate requests are queue to execute.

[How]
In case of 12 VF increase timeout on 12*100ms

Signed-off-by: Dusica Milinkovic &lt;Dusica.Milinkovic@amd.com&gt;
Acked-by: Shaoyun Liu &lt;shaoyun.liu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix the incomplete product number</title>
<updated>2022-07-28T20:05:14Z</updated>
<author>
<name>Roy Sun</name>
<email>Roy.Sun@amd.com</email>
</author>
<published>2022-07-20T08:19:50Z</published>
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<id>urn:sha1:1f83db6be37c53f6d395a41ee2602e3280ee60c2</id>
<content type='text'>
The comments say that the product number is a 16-digit HEX string so the
buffer needs to be at least 17 characters to hold the NUL terminator. Expand
the buffer size to 20 to avoid the alignment issues.

The comment:Product number should only be 16 characters. Any
more,and something could be wrong. Cap it at 16 to be safe

Signed-off-by: Roy Sun &lt;Roy.Sun@amd.com&gt;
Reviewed-by: André Almeida &lt;andrealmeid@igalia.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add visualconfirm module parameter</title>
<updated>2022-07-25T13:31:03Z</updated>
<author>
<name>Leo Li</name>
<email>sunpeng.li@amd.com</email>
</author>
<published>2022-07-06T18:48:52Z</published>
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<id>urn:sha1:792a0cdde34d417bc2c8266d8015c5fd58d44a0d</id>
<content type='text'>
[Why]

Being able to configure visual confirm at boot or in cmdline is helpful
when debugging.

[How]

Add a module parameter to configure DC visual confirm, which works the
same way as the equivalent debugfs entry.

Signed-off-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: drop runpm from amdgpu_device structure</title>
<updated>2022-07-18T20:42:39Z</updated>
<author>
<name>Guchun Chen</name>
<email>guchun.chen@amd.com</email>
</author>
<published>2022-07-14T08:37:29Z</published>
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<id>urn:sha1:9c913f38032e873758d1b13fce720a0c2cbbfcb7</id>
<content type='text'>
It's redundant, as now switching to rpm_mode to indicate
runtime power management mode.

Suggested-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: support reset flag set for gpu reset</title>
<updated>2022-07-13T15:25:17Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2022-07-08T03:14:05Z</published>
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<id>urn:sha1:f1549c09c520877be211d483d3c6f4e7f77d2588</id>
<content type='text'>
Move reset_context out of gpu recover function to make it configurable
for different reset purpose.
For the reset way of call gpu_recovery sysfs, force to use full reset
method. Otherwise, try soft reset by default if the related ASIC
supportted, if soft reset failed, will use full reset.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Rename amdgpu_device_gpu_recover_imp back to amdgpu_device_gpu_recover</title>
<updated>2022-06-10T19:26:12Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2022-05-17T18:27:49Z</published>
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<id>urn:sha1:cf727044144d47c3e8482b9a7775bd3f04a87341</id>
<content type='text'>
We removed the wrapper that was queueing the recover function
into reset domain queue who was using this name.

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add work_struct for GPU reset from debugfs</title>
<updated>2022-06-10T19:25:48Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2022-05-17T18:14:19Z</published>
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<id>urn:sha1:2f83658ffc8c259f05e79dc632e34b26bb8b75c5</id>
<content type='text'>
We need to have a work_struct to cancel this reset if another
already in progress.

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable ASPM support for PCIE 7.4.0/7.6.0</title>
<updated>2022-06-08T15:43:00Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2022-04-28T08:51:04Z</published>
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<id>urn:sha1:62f8f5c3bfc2968461b0a74f0e393325bec16c69</id>
<content type='text'>
Enable ASPM support for PCIE 7.4.0 and 7.6.0.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add peer-to-peer support among PCIe connected AMD GPUs</title>
<updated>2022-06-08T15:40:12Z</updated>
<author>
<name>Ramesh Errabolu</name>
<email>Ramesh.Errabolu@amd.com</email>
</author>
<published>2022-05-26T17:24:23Z</published>
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<id>urn:sha1:08a2fd23c6c21e5ef24248a9c1b09e929655eb3b</id>
<content type='text'>
Add support for peer-to-peer communication among AMD GPUs over PCIe
bus. Support REQUIRES enablement of config HSA_AMD_P2P.

Signed-off-by: Ramesh Errabolu &lt;Ramesh.Errabolu@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: adding device coredump support</title>
<updated>2022-06-06T18:41:19Z</updated>
<author>
<name>Somalapuram Amaranath</name>
<email>Amaranath.Somalapuram@amd.com</email>
</author>
<published>2022-06-02T07:31:27Z</published>
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<id>urn:sha1:3d8785f6c04a953868384db455bb2fdd0b22c11c</id>
<content type='text'>
Added device coredump information:
- Kernel version
- Module
- Time
- VRAM status
- Guilty process name and PID
- GPU register dumps
v1 -&gt; v2: Variable name change
v1 -&gt; v2: NULL check
v1 -&gt; v2: Code alignment
v1 -&gt; v2: Adding dummy amdgpu_devcoredump_free
v1 -&gt; v2: memset reset_task_info to zero
v2 -&gt; v3: add CONFIG_DEV_COREDUMP for variables
v2 -&gt; v3: remove NULL check on amdgpu_devcoredump_read

Signed-off-by: Somalapuram Amaranath &lt;Amaranath.Somalapuram@amd.com&gt;
Reviewed-by: Shashank Sharma &lt;Shashank.sharma@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
